The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
完整性高的FPGA-PCB系統化協同設計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復雜的設計及在設計初級產生最佳的I/O引腳規劃，并可透過FSP做系統化的設計規劃，同時整合logic、schematic、PCB同步規劃單個或多個FPGA pin的最佳化及layout placement，借由整合式的界面以減少重復在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節省更多的走線空間或疊構。 Specifying Design Intent 在FSP整合工具內可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內的包裝，預先讓我們同步規劃FPGA設計及在PCB的placement。
標簽： Allegro Planner System FPGA
上傳時間： 2013-11-06
上傳用戶：wwwe
GSM是Global System For Mobile Communications的縮寫。由歐洲電信標準組織ETSI制訂的一個數字移動通信標準。GSM是全球移動通信系統(Global System of Mobile communication) 的簡稱。它的空中接口采用時分多址技術。
上傳時間： 2013-10-09
上傳用戶：1142895891
for 51 for arm
上傳時間： 2013-10-10
上傳用戶：xiaoyuer
Aspen Plus介紹 (物性數據庫) · Aspen Plus ---生產裝置設計、穩態模擬和優化的大型通用流程模擬系統 · Aspen Plus是大型通用流程模擬系統，源于美國能源部七十年代后期在麻省理工學院(MIT)組織的會 戰，開發新型第三代流程模擬軟件。該項目稱為“過程工程的先進系統”(Advanced System for Process Engineering，簡稱ASPEN),并于1981年底完成。1982年為了將其商品化，成立了AspenTech公司，并稱之為Aspen Plus。該軟件經過20多年來不斷地改進、擴充和提高，已先后推出了十多個版本，成為舉世公認的標準大型流程模擬軟件，應用案例數以百萬計。全球各大化工、石化、煉油等過程工業制造企業及著名的工程公司都是Aspen Plus的用戶。 它以嚴格的機理模型和先進的技術贏得廣大用戶的信賴，它具有以下特性： 1. ASPEN PLUS有一個公認的跟蹤記錄，在一個工藝過程的制造的整個生命周期中提供巨大的經濟效益，制造生命周期包括從研究與開發經過工程到生產。 2. ASPEN PLUS使用最新的軟件工程技術通過它的Microsoft Windows圖形界面和交互式客戶-服務器模擬結構使得工程生產力最大。 3. ASPEN PLUS擁有精確模擬范圍廣泛的實際應用所需的工程能力， 這些實際應用包括從煉油到非理想化學系統到含電解質和固體的工藝過程。 4. ASPEN PLUS是AspenTech的集成聰明制造系統技術的一個核心部分， 該技術能在你公司的整個過程工程基本設施范圍內捕獲過程專業知識并充分利用。 在實際應用中，ASPEN PLUS可以幫助工程師解決快速閃蒸計算、設計一個新的工藝過程、查找一個原油加工裝置的故障或者優化一個乙烯全裝置的操作等工程和操作的關鍵問。
上傳時間： 2013-11-16
上傳用戶：我干你啊
for 51 for arm
上傳時間： 2013-11-14
上傳用戶：huql11633
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
完整性高的FPGA-PCB系統化協同設計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復雜的設計及在設計初級產生最佳的I/O引腳規劃，并可透過FSP做系統化的設計規劃，同時整合logic、schematic、PCB同步規劃單個或多個FPGA pin的最佳化及layout placement，借由整合式的界面以減少重復在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節省更多的走線空間或疊構。 Specifying Design Intent 在FSP整合工具內可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內的包裝，預先讓我們同步規劃FPGA設計及在PCB的placement。
標簽： Allegro Planner System FPGA
上傳時間： 2013-10-19
上傳用戶：shaojie2080
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-14
上傳用戶：zoudejile
通過以太網遠程配置Nios II 處理器 應用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上傳時間： 2013-11-22
上傳用戶：chaisz
