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cross-platform

  • WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案

    WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 :Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.

    標(biāo)簽: 369 WP 擴展式 處理平臺

    上傳時間: 2013-10-22

    上傳用戶:685

  • xilinx Zynq-7000 EPP產(chǎn)品簡介

    The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously. 

    標(biāo)簽: xilinx Zynq 7000 EPP

    上傳時間: 2013-11-01

    上傳用戶:dingdingcandy

  • WP253 - 簡化FPGA配置設(shè)計過程

      本文著重介紹了 Xilinx Platform Flash PROM 如何幫助系統(tǒng)和電路板設(shè)計人員簡化 FPGA 配置設(shè)計。用于配置 FPGA 的可選解決方案有很多,但它們通常都需要大量的前期設(shè)計工作和時間。Platform Flash 是為配置 Xilinx FPGA 專門設(shè)計的一款包括硬件和軟件支持在內(nèi)的整體解決方案。

    標(biāo)簽: FPGA 253 WP 過程

    上傳時間: 2013-11-04

    上傳用戶:ifree2016

  • 基于FPGA+DSP模式的智能相機設(shè)計

    針對嵌入式機器視覺系統(tǒng)向獨立化、智能化發(fā)展的要求,介紹了一種嵌入式視覺系統(tǒng)--智能相機。基于對智能相機體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析,對國內(nèi)外的幾款智能相機進行比較。綜合技術(shù)發(fā)展現(xiàn)狀,提出基于FPGA+DSP模式的硬件平臺,并提出智能相機的發(fā)展方向。分析結(jié)果表明,該系統(tǒng)設(shè)計可以實現(xiàn)脫離PC運行,完成圖像獲取與分析,并作出相應(yīng)輸出。 Abstract:  This paper introduced an embedded vision system-intelligent camera ,which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture, component modules and image acquisition, transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad, the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design, the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

    標(biāo)簽: FPGA DSP 模式 智能相機

    上傳時間: 2013-10-24

    上傳用戶:bvdragon

  • 基于CPLD的QDPSK調(diào)制解調(diào)電路設(shè)計

    為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式,在分析四相相對移相(QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上,設(shè)計了一種QDPSK調(diào)制解調(diào)電路,它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上,進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中,測試結(jié)果表明,調(diào)制電路能正確選相,解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致,達到了預(yù)期的設(shè)計要求。 Abstract:  In order to realize the better application of digital modulation mode QDPSK in the CDMA system, a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase,and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

    標(biāo)簽: QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計

    上傳時間: 2014-01-13

    上傳用戶:qoovoop

  • ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼

    ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼 Description:   Contains the following files     readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform:   All Installation/Use:   Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

    標(biāo)簽: xilinx SRAM VHDL ZBT

    上傳時間: 2013-11-24

    上傳用戶:31633073

  • 基于云計算的蒙特卡羅模擬分析

    為了提高蒙特卡羅模擬分析的效率,設(shè)計了一種以Platform Symphony為基礎(chǔ)的云計算平臺,并對平臺進行了擴展和集成,詳細論述了實現(xiàn)的過程以及關(guān)鍵技術(shù)。通過實驗表明,該平臺能夠進行高性能計算,輸出的結(jié)果精確,是實現(xiàn)蒙特卡羅模擬分析的實用工具。

    標(biāo)簽: 云計算 蒙特卡羅 模擬分析

    上傳時間: 2013-12-22

    上傳用戶:kangqiaoyibie

  • XAPP807-封裝最小的三態(tài)以太網(wǎng)MAC處理引擎

    The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.

    標(biāo)簽: XAPP 807 MAC 封裝

    上傳時間: 2013-10-26

    上傳用戶:yuzsu

  • 基于以太網(wǎng)的虛擬示波器設(shè)計

    為提升虛擬儀器傳輸速率與實時性能,擴展監(jiān)測范圍,在VC的軟件平臺上設(shè)計了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比,該系統(tǒng)采用嵌入式系統(tǒng)完成信號采集,采用工業(yè)以太網(wǎng)為傳輸介質(zhì),通過線性插值算法和多線程編程思想,實現(xiàn)波形顯示、參數(shù)計算、頻譜分析以及波形存儲及回放功能。實驗結(jié)果表明,該虛擬示波器可以實現(xiàn)20 kHz采樣頻率下的波形精確顯示,達到預(yù)期的各項指標(biāo)。 Abstract:  o enhance the transfer rate and real-time of virtual instrument performance, expand scope of monitoring, this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope, this system adopts the embedded system to complete the data acquisition, industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas, namely to achieve waveform display, parameter calculation, spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency, and achieve the desired targets.

    標(biāo)簽: 以太網(wǎng) 虛擬 波器設(shè)計

    上傳時間: 2013-11-25

    上傳用戶:wbwyl

  • 數(shù)據(jù)分析儀說明書

    User ManualRev. 1.2SmartRF® CC2420DK: Packet Sniffer for IEEE 802.15.4 and ZigBee Table of contents1 INTRODUCTION...............................................................................................31.1 HARDWARE PLATFORM.......................................................................................31.2 SOFTWARE.........................................................................................................32 USER INTERFACE..........................................................................................42.1 MENUS AND TOOLBARS.......................................................................................62.2 SETUP................................................................................................................62.3 SELECT FIELDS...................................................................................................72.3.1 Tips............................................................................................................72.4 PACKET DETAILS.................................................................................................72.5 ADDRESS BOOK..................................................................................................92.5.1 Tips............................................................................................................92.6 DISPLAY FILTER................................................................................................102.7 TIME LINE.........................................................................................................103 HELP....................................................................................................................114 TROUBLESHOOTING..................................................................................125 GENERAL INFORMATION........................................................................135.1 DOCUMENT HISTORY........................................................................................135.2 DISCLAIMER......................................................................................................135.3 TRADEMARKS...................................................................................................136 ADDRESS INFORMATION........................................................................14

    標(biāo)簽: 數(shù)據(jù) 分析儀 說明書

    上傳時間: 2014-01-14

    上傳用戶:zhangyi99104144

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