PC機(jī)之間串口通信的實(shí)現(xiàn)一、實(shí)驗(yàn)?zāi)康?nbsp;１．熟悉微機(jī)接口實(shí)驗(yàn)裝置的結(jié)構(gòu)和使用方法。 ２．掌握通信接口芯片8251和8250的功能和使用方法。 ３．學(xué)會(huì)串行通信程序的編制方法。 二、實(shí)驗(yàn)內(nèi)容與要求 １．基本要求主機(jī)接收開(kāi)關(guān)量輸入的數(shù)據(jù)（二進(jìn)制或十六進(jìn)制），從鍵盤(pán)上按“傳輸”鍵（可自行定義），就將該數(shù)據(jù)通過(guò)8251A傳輸出去。終端接收后在顯示器上顯示數(shù)據(jù)。具體操作說(shuō)明如下：（１）出現(xiàn)提示信息“start with R in the board!”，通過(guò)調(diào)整乒乓開(kāi)關(guān)的狀態(tài)，設(shè)置8位數(shù)據(jù)；（２）在小鍵盤(pán)上按“R”鍵，系統(tǒng)將此時(shí)乒乓開(kāi)關(guān)的狀態(tài)讀入計(jì)算機(jī)I中，并顯示出來(lái)，同時(shí)顯示經(jīng)串行通訊后，計(jì)算機(jī)II接收到的數(shù)據(jù)；（３）完成后，系統(tǒng)提示“do you want to send another data? Y/N”，根據(jù)用戶需要，在鍵盤(pán)按下“Y”鍵，則重復(fù)步驟（1），進(jìn)行另一數(shù)據(jù)的通訊；在鍵盤(pán)按除“Y”鍵外的任意鍵，將退出本程序。２．提高要求 能夠進(jìn)行出錯(cuò)處理，例如采用奇偶校驗(yàn)，出錯(cuò)重傳或者采用接收方回傳和發(fā)送方確認(rèn)來(lái)保證發(fā)送和接收正確。 三、設(shè)計(jì)報(bào)告要求 １．設(shè)計(jì)目的和內(nèi)容 ２．總體設(shè)計(jì) ３．硬件設(shè)計(jì)：原理圖（接線圖）及簡(jiǎn)要說(shuō)明 ４．軟件設(shè)計(jì)框圖及程序清單５．設(shè)計(jì)結(jié)果和體會(huì)（包括遇到的問(wèn)題及解決的方法） 四、8251A通用串行輸入/輸出接口芯片由于CPU與接口之間按并行方式傳輸，接口與外設(shè)之間按串行方式傳輸，因此，在串行接口中，必須要有“接收移位寄存器”（串→并）和“發(fā)送移位寄存器”（并→串）。能夠完成上述“串←→并”轉(zhuǎn)換功能的電路，通常稱為“通用異步收發(fā)器”（UART：Universal Asynchronous Receiver and Transmitter）,典型的芯片有：Intel 8250/8251。8251A異步工作方式：如果8251A編程為異步方式，在需要發(fā)送字符時(shí)，必須首先設(shè)置TXEN和CTS#為有效狀態(tài)，TXEN(Transmitter Enable)是允許發(fā)送信號(hào)，是命令寄存器中的一位；CTS#(Clear To Send)是由外設(shè)發(fā)來(lái)的對(duì)CPU請(qǐng)求發(fā)送信號(hào)的響應(yīng)信號(hào)。然后就開(kāi)始發(fā)送過(guò)程。在發(fā)送時(shí)，每當(dāng)CPU送往發(fā)送緩沖器一個(gè)字符，發(fā)送器自動(dòng)為這個(gè)字符加上1個(gè)起始位，并且按照編程要求加上奇／偶校驗(yàn)位以及1個(gè)、1.5個(gè)或者2個(gè)停止位。串行數(shù)據(jù)以起始位開(kāi)始，接著是最低有效數(shù)據(jù)位，最高有效位的后面是奇／偶校驗(yàn)位，然后是停止位。按位發(fā)送的數(shù)據(jù)是以發(fā)送時(shí)鐘TXC的下降沿同步的，也就是說(shuō)這些數(shù)據(jù)總是在發(fā)送時(shí)鐘TXC的下降沿從8251A發(fā)出。數(shù)據(jù)傳輸?shù)牟ㄌ芈嗜Q于編程時(shí)指定的波特率因子，為發(fā)送器時(shí)鐘頻率的1、1/16或1/64。當(dāng)波特率指定為16時(shí)，數(shù)據(jù)傳輸?shù)牟ㄌ芈示褪前l(fā)送器時(shí)鐘頻率的1/16。CPU通過(guò)數(shù)據(jù)總線將數(shù)據(jù)送到8251A的數(shù)據(jù)輸出緩沖寄存器以后，再傳輸?shù)桨l(fā)送緩沖器，經(jīng)移位寄存器移位，將并行數(shù)據(jù)變?yōu)榇袛?shù)據(jù)，從TxD端送往外部設(shè)備。在8251A接收字符時(shí)，命令寄存器的接收允許位RxE(Receiver Enable)必須為1。8251A通過(guò)檢測(cè)RxD引腳上的低電平來(lái)準(zhǔn)備接收字符，在沒(méi)有字符傳送時(shí)RxD端為高電平。8251A不斷地檢測(cè)RxD引腳，從RxD端上檢測(cè)到低電平以后，便認(rèn)為是串行數(shù)據(jù)的起始位，并且啟動(dòng)接收控制電路中的一個(gè)計(jì)數(shù)器來(lái)進(jìn)行計(jì)數(shù)，計(jì)數(shù)器的頻率等于接收器時(shí)鐘頻率。計(jì)數(shù)器是作為接收器采樣定時(shí)，當(dāng)計(jì)數(shù)到相當(dāng)于半個(gè)數(shù)位的傳輸時(shí)間時(shí)再次對(duì)RxD端進(jìn)行采樣，如果仍為低電平，則確認(rèn)該數(shù)位是一個(gè)有效的起始位。若傳輸一個(gè)字符需要16個(gè)時(shí)鐘，那么就是要在計(jì)數(shù)8個(gè)時(shí)鐘后采樣到低電平。之后，8251A每隔一個(gè)數(shù)位的傳輸時(shí)間對(duì)RxD端采樣一次，依次確定串行數(shù)據(jù)位的值。串行數(shù)據(jù)位順序進(jìn)入接收移位寄存器，通過(guò)校驗(yàn)并除去停止位，變成并行數(shù)據(jù)以后通過(guò)內(nèi)部數(shù)據(jù)總線送入接收緩沖器，此時(shí)發(fā)出有效狀態(tài)的RxRDY信號(hào)通知CPU，通知CPU8251A已經(jīng)收到一個(gè)有效的數(shù)據(jù)。一個(gè)字符對(duì)應(yīng)的數(shù)據(jù)可以是5～8位。如果一個(gè)字符對(duì)應(yīng)的數(shù)據(jù)不到8位，8251A會(huì)在移位轉(zhuǎn)換成并行數(shù)據(jù)的時(shí)候，自動(dòng)把他們的高位補(bǔ)成0。 五、系統(tǒng)總體設(shè)計(jì)方案根據(jù)系統(tǒng)設(shè)計(jì)的要求，對(duì)系統(tǒng)設(shè)計(jì)的總體方案進(jìn)行論證分析如下：1．獲取8位開(kāi)關(guān)量可使用實(shí)驗(yàn)臺(tái)上的8255A可編程并行接口芯片，因?yàn)橹灰@取8位數(shù)據(jù)量，只需使用基本輸入和8位數(shù)據(jù)線，所以將8255A工作在方式0，PA0-PA7接實(shí)驗(yàn)臺(tái)上的8位開(kāi)關(guān)量。2．當(dāng)使用串口進(jìn)行數(shù)據(jù)傳送時(shí)，雖然同步通信速度遠(yuǎn)遠(yuǎn)高于異步通信，可達(dá)500kbit/s，但由于其需要有一個(gè)時(shí)鐘來(lái)實(shí)現(xiàn)發(fā)送端和接收端之間的同步，硬件電路復(fù)雜，通常計(jì)算機(jī)之間的通信只采用異步通信。3．由于8251A本身沒(méi)有時(shí)鐘，需要外部提供，所以本設(shè)計(jì)中使用實(shí)驗(yàn)臺(tái)上的8253芯片的計(jì)數(shù)器2來(lái)實(shí)現(xiàn)。4：顯示和鍵盤(pán)輸入均使用DOS功能調(diào)用來(lái)實(shí)現(xiàn)。設(shè)計(jì)思路框圖，如下圖所示： 六、硬件設(shè)計(jì)硬件電路主要分為8位開(kāi)關(guān)量數(shù)據(jù)獲取電路，串行通信數(shù)據(jù)發(fā)送電路，串行通信數(shù)據(jù)接收電路三個(gè)部分。1．8位開(kāi)關(guān)量數(shù)據(jù)獲取電路該電路主要是利用8255并行接口讀取8位乒乓開(kāi)關(guān)的數(shù)據(jù)。此次設(shè)計(jì)在獲取8位開(kāi)關(guān)數(shù)據(jù)量時(shí)采用8255令其工作在方式0，A口輸入8位數(shù)據(jù)，CS#接實(shí)驗(yàn)臺(tái)上CS1口，對(duì)應(yīng)端口為280H-283H，PA0-PA7接8個(gè)開(kāi)關(guān)。2．串行通信電路串行通信電路本設(shè)計(jì)中8253主要為8251充當(dāng)頻率發(fā)生器，接線如下圖所示。
上傳時(shí)間： 2013-12-19
上傳用戶：小火車(chē)?yán)怖怖?/p>
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標(biāo)簽： routines slave I2C 87L
上傳時(shí)間： 2013-11-19
上傳用戶：shirleyYim
本文介紹使用AT89C2051 制作的一種發(fā)音電路, 各種聲音通過(guò)編程實(shí)現(xiàn), 靈活方便。原理圖如圖1 所示。圖1 發(fā)音電路原理該電路利用方波諧波成份豐富的特點(diǎn),編程采用計(jì)時(shí)器延遲法發(fā)音, 即每個(gè)音的半周期計(jì)時(shí)中斷一次, 而使輸出P110 (或其他IöO 口) 反相, 重復(fù)執(zhí)行產(chǎn)生某種頻率的信號(hào)。例如: 中音DO 的頻率為523Hz, 其周期為1912Ls, 半周期為956Ls, 若初始P110= 1, 經(jīng)956Ls 后應(yīng)使P110= 0, 再經(jīng)956Ls 恢復(fù)P110= 1, 這樣就可發(fā)出中音DO。
上傳時(shí)間： 2013-10-11
上傳用戶：Altman
第1章 單片機(jī)系統(tǒng)概述1.1 AVR系列單片機(jī)的特點(diǎn)1.2 AT90系列單片機(jī)簡(jiǎn)介第2章 AT90LS8535單片機(jī)的基礎(chǔ)知識(shí)2.1 AT90LS8535單片機(jī)的總體結(jié)構(gòu)2.1.1 AT90LS8535單片機(jī)的中央處理器2.1.2 AT90LS8535單片機(jī)的存儲(chǔ)器組織2.1.3 AT90LS8535單片機(jī)的I/O接口2.1.4 AT90LS8535單片機(jī)的內(nèi)部資源2.1.5 AT90LS8535單片機(jī)的時(shí)鐘電路2.1.6 AT90LS8535單片機(jī)的系統(tǒng)復(fù)位2.1.7 AT90LS8535單片機(jī)的節(jié)電方式2.1.8 AT90LS8535單片機(jī)的芯片引腳2.2 AT90LS8535單片機(jī)的指令系統(tǒng)2.2.1 匯編指令格式2.2.2 尋址方式2.2.3 偽指令2.2.4 指令類型及數(shù)據(jù)操作方式2.3 應(yīng)用程序設(shè)計(jì)2.3.1 程序設(shè)計(jì)方法2.3.2 應(yīng)用程序舉例第3章 AT90LS8535單片機(jī)的C編程3.1 支持高級(jí)語(yǔ)言編程的AVR系列單片機(jī)3.2 AVR的C編譯器3.3 ICC AVR介紹3.3.1 安裝ICC AVR3.3.2 設(shè)置ICC AVR3.4 用ICC AVR編寫(xiě)應(yīng)用程序3.5 下載程序文件第4章 數(shù)據(jù)類型、運(yùn)算符和表達(dá)式4.1 ICC AVR支持的數(shù)據(jù)類型4.2 常量與變量4.2.1 常量4.2.2 變量4.3 AT90LS8535的存儲(chǔ)空間4.4 算術(shù)和賦值運(yùn)算4.4.1 算術(shù)運(yùn)算符和算術(shù)表達(dá)式4.4.2 賦值運(yùn)算符和賦值表達(dá)式4.5 邏輯運(yùn)算4.6 關(guān)系運(yùn)算4.7 位操作4.7.1 位邏輯運(yùn)算4.7.2 移位運(yùn)算4.8 逗號(hào)運(yùn)算第5章 控制流5.1 C語(yǔ)言的結(jié)構(gòu)化程序設(shè)計(jì)5.1.1 順序結(jié)構(gòu)5.1.2 選擇結(jié)構(gòu)5.1.3 循環(huán)結(jié)構(gòu)5.2 選擇語(yǔ)句5.2.1 if語(yǔ)句5.2.2 switch分支5.2.3 選擇語(yǔ)句的嵌套5.3 循環(huán)語(yǔ)句5.3.1 while語(yǔ)句5.3.2 do…while語(yǔ)句5.3.3 for語(yǔ)句5.3.4 循環(huán)語(yǔ)句嵌套5.3.5 break語(yǔ)句和continue語(yǔ)句第6章 函數(shù)6.1 函數(shù)的定義6.1.1 函數(shù)的定義的一般形式6.1.2 函數(shù)的參數(shù)6.1.3 函數(shù)的值6.2 函數(shù)的調(diào)用6.2.1 函數(shù)的一般調(diào)用6.2.2 函數(shù)的遞歸調(diào)用6.2.3 函數(shù)的嵌套使用6.3 變量的類型及其存儲(chǔ)方式6.3.1 局部變量6.3.2 局部變量的存儲(chǔ)方式6.3.3 全局變量6.3.4 全局變量的存儲(chǔ)方式6.4 內(nèi)部函數(shù)和外部函數(shù)6.4.1 內(nèi)部函數(shù)6.4.2 外部函數(shù)第7章 指針第8章 結(jié)構(gòu)體和共用體第9章 AT90LS8535的內(nèi)部資源第10章 AT90LS8535的人機(jī)接口編程第11章 AT90LS8535的外圍擴(kuò)展第12章 AT90LS8535的通信編程第13章 系統(tǒng)設(shè)計(jì)中的程序處理方法
標(biāo)簽： avr 單片機(jī)c語(yǔ)言
上傳時(shí)間： 2013-10-31
上傳用戶：smthxt
載波相移正弦脈寬調(diào)制（SPWM）技術(shù)是一種適用于大功率電力開(kāi)關(guān)變換裝置的高性能開(kāi)關(guān)調(diào)制策略，在有源電力濾波器中有良好的應(yīng)用前景。本文介紹了如何利用高性能數(shù)字信號(hào)處理器TMS320F28335的片內(nèi)外設(shè)事件管理器（EV）模塊產(chǎn)生三相SPWM波，給出了程序流程圖及關(guān)鍵程序源碼。該方法采用不對(duì)稱規(guī)則采樣算法，參數(shù)計(jì)算主要采用查表法，計(jì)算量小，實(shí)時(shí)性高。在工程實(shí)踐中表明，該方法既能滿足控制精度要求，又能滿足實(shí)時(shí)性要求，可以很好地控制逆變電源的輸出。
標(biāo)簽： F28335 28335 SPWM 320F
上傳時(shí)間： 2013-11-05
上傳用戶：tzrdcaabb
There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.
標(biāo)簽： Xilinx 便攜式 超聲系統(tǒng) 器件
上傳時(shí)間： 2013-10-26
上傳用戶：liulinshan2010
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時(shí)間： 2013-10-29
上傳用戶：lixqiang
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-07
上傳用戶：jasson5678
The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8! Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects! This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽： Everyone LabVIEW for 英文
上傳時(shí)間： 2013-10-14
上傳用戶：shawvi
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
