Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時間： 2013-11-10
上傳用戶：yy_cn
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上傳時間： 2013-11-23
上傳用戶：nanxia
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上傳時間： 2013-11-01
上傳用戶：xzt
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時間： 2013-10-22
上傳用戶：lmq0059
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上傳時間： 2013-11-02
上傳用戶：18862121743
RSM是廣州致遠電子有限公司全新系列的基于RS-485接口的數據采集模塊。RSM數據采集模塊在單個設備中集成了I/O、數據采集和隔離的RS-485總線接口。支持標準的Modbus協議和自定義ASCII協議。RSM-7404是計數/測頻模塊，具有4路32位計數/測頻通道，其中包括2路隔離通道和2路非隔離通道，以滿足不同場合需求；模塊還具有4路的DO通道和4路DI通道；模塊還支持編碼器輸入功能，可直接連接編碼器信號進行角度和轉速計算。RSM-7404采用帶隔離的RS-485總線接口及看門狗技術，有效保障設備安全可靠運行。
上傳時間： 2013-11-07
上傳用戶：魚哥哥你好
我近期計劃陸續整理出以下幾個方面的學習筆記：初學 ModelSimSE 時被迷糊了幾天的若干概念；在 ModelSimSE 中添加 ALTERA 仿真庫的詳細步驟；用 ModelSimSE 進行功能仿真和時序仿真的方法（ALTERA 篇）；ModelSimSE 中常用到的幾個命令及 DO文件的學習筆記；近來學到的幾招 TestBench 的技巧
上傳時間： 2013-10-13
上傳用戶：18602424091
eGroupWare is a multi-user, web-based groupware suite developed on a custom set of PHP-based APIs. Currently available modules include: email, addressbook, calendar, infolog (notes, to-do s, phone calls), content management, forum, bookmarks, wiki
標簽： eGroupWare multi-user developed PHP-based
上傳時間： 2015-02-20
上傳用戶：hphh
軟件測試：一個編譯器測試軟件，支持下列C語言運算符：+ - * / % ^（乘方） 負 (int) (double) "字符串" []（數組） > < == >= <= != && ! ++ -- = += -= *= /= %= ^=，支持下列關鍵字：void int double string if else for while do goto break continue return，支持下列數據類型：int double string int[] double[] string[]，支持下列系統函數：int max(int,int)，double max(double,double)，int[] newint(int)，double[] newdouble(int)，string[] newstring(int)，void delete(int[])，void delete(double[])，void delete(string[])，支持任意用戶定義函數，支持函數重載。不支持全局變量。如果發現錯誤，請告訴我
上傳時間： 2013-12-15
上傳用戶：sy_jiadeyi
