Fast settling-time added to the already conflicting requirements of narrow channel spacing and
low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
標(biāo)簽：
settling-time
requirements
conflicting
already
上傳時(shí)間：
2016-04-14
上傳用戶：liansi
