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it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

標簽： synthesize simulator modelsim interin

上傳時間： 2017-03-22

上傳用戶：洛木卓