it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
標(biāo)簽: synthesize simulator modelsim interin
上傳時(shí)間: 2017-03-22
上傳用戶:洛木卓
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1