<samp id="omqi2"></samp> FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
Multisim官方示例Multisim仿真例程基礎電路范例135例合集:Chapter 1 - RLC CircuitsChapter 2 - DiodesChapter 3 - TransistorsChapter 4 - AmplifiersChapter 5 - OpampsChapter 6 - FiltersChapter 7 - Miscellaneous CircuitsFundamental Circuits.pdf004 Parallel DC Circuits.ms10005 Series-Parrallel DC Circuit.ms10006 Current Analysis.ms10007 Millmans Theorem 1.ms10008 Millmans Theorem 2.ms10009 Kirchhoff's Current Law.ms10010 Thevenin's Theorem.ms10011 Superposition Principle.ms10012 Nortons Theorem and Source Conversion.ms10013 AC Voltage Measurement.ms10014 Frequency Response of the Series RL Network.ms10015 RL High and Low Pass Filter.ms10016 Frequency Response of the Series RC Network.ms10017 RC High and Low Pass Filter.ms10019 Center-Tapped Full-Wave Rectifier.ms10020 Bridge Rectifier.ms10021 Capacitor-Input Rectifier Filter.ms10022 Diode Clipper (Limiter).ms10023 Diode Clipper.ms10024 Diode Clamper (DC Restorer).ms10025 Diode Voltage Doubler.ms10026 Zener Diode and Voltage Regulation 1.ms10027 Zener Diode and Voltage Regulation 2.ms10028 Zener Diode and Voltage Regulation 3.ms10105 TTL Inverter.ms10107 TTL Gate.ms10109 OR Gate Circuit.ms10111 Over-Damp Circuit.ms10113 Critical-Damp Circuit.ms10115 Series RLC Circuit 1.ms10117 Clapp Oscillator.ms10119 Differential Amplifier 1.ms10121 Differential Amplifier in Common Mode.ms10123 LC Oscillator with Unity Gain Buffer.ms10125 Notch Filter.ms10127 PNP Differential Pair.ms10129 Crossover Network.ms10131 Second-Order High-Pass Chebyshev Filter.ms10133 Third-Order High-Pass Chebyshev Filter.ms10135 Fifth-Order High-Pass Filter.ms10
標簽： multisim
上傳時間： 2021-10-27
上傳用戶：trh505
國外大牛寫的電源控制仿真模型，講解很詳細。
標簽： 電源控制仿真模型
上傳時間： 2021-11-03
上傳用戶：kent
基于cubeMX的stm32L0系列單片機RTC配置及相關寄存器配置代碼，可用于低功耗模式下（stop mode）對單片機進行喚醒，無需外部喚醒源，只需配置RTC的內部喚醒功能即可實現，代碼親測可用。
上傳時間： 2021-11-16
上傳用戶：
USB_MICRO USB_MNI USB扁口座 TF卡槽 SOIC8 LQFP32芯片ALTIUM 庫（3D PCB封裝庫）, 3D封裝，已在項目中使用，可以做為你的設計參考。詳細列表如下：Component Count : 94Component Name-----------------------------------------------32165032-8MHZAMS1117ANT2AntennaBATbuzzerCapCAP-0805CAP-3216CD32Crystal Oscillator 3225HC-06KEY-2PINLED-0603LQFP-100LQFP32LQFP44LQFP44 10X10_LLQFP44 10X10_MLQFP44 10X10_NLQFP48LQFP48 7X7_LLQFP48 7X7_MLQFP48 7X7_NLQFP64 10x10_LLQFP64 10x10_MLQFP64 10x10_NMagMOTONRF24L01NRF24L01-modeOLED-0.96-PIN7QFN20_4X4QFN24_4X4QFN32_5X5remoteRES-0603RFX2401CRPSG90SH1.0mm-4PINSH1.0MM-5PINSH1.0mm-6PINSMA-ANTSMA/DO-214SOIC-8SOP16SOT-23-3SOT-23-5SOT-89SOT-223SPL06-001STM32F030C8T6STM32F030F4P6STM32F103C8T6straight-1x2pinstraight-1x2pin - duplicatestraight-1x2pin - duplicate1straight-1x3pinstraight-1x3pin - duplicatestraight-1x3pin - duplicate1straight-1x4pinstraight-1x4pin - duplicatestraight-1x5pinstraight-1x8pinstraight-1x8pin - duplicatestraight-2x2pinstraight-2x3pinstraight-2x4pinstraight-2x5pinSW-NO/OFF-PIN3SW-SMD1SW-SMD2SWITCH-DIP-6*6*7SX1308TF-CARDTO-263-5TP4056USBUSB_MICROUSB_MNI_BUSB-MICRO-1winding_1x2pinwinding_1x3pinwinding_1x4pinwinding_1x5pinwinding_1x8pinwinding_2x2pinwinding_2x3pinwinding_2x4pinwinding_2x5pinXTAL-5070/SMDXTAL-QC49/SMD
標簽： usb
上傳時間： 2021-12-02
上傳用戶：aben
NCP1399 是高性能電流模式控制器，半橋諧 變換器。此控制器實現 600 V 門驅動、 簡化布 局和減少外部組件計數 。built - in 和 Brown - Out 輸入函數簡化了執行在所有應用程序的控制器。 在 PFC 前階段的應用 NCP1399 需要設有專用的 輸出驅動 PFC 前級控制器。此功能專用 skip-mode 技術進一步提高輕負載效率的整個應 用程序。 NCP1399 提供全套的保護功能允許安全 運行在任何應用程序中。這包括：過載保護，過 流保護以防止硬開關周期， brown- out 檢測，打 開光電耦合器檢測， 死區自動調整， 過電壓（OVP） 和 (OTP) 過溫保護
上傳時間： 2021-12-17
上傳用戶：qingfengchizhu
HI3520DV400全套資料（Cadence arregro原理圖+PCB+bom+鏡像軟件），1個HDMI輸入，1個HDMI輸出，1個3.5音頻輸入，1個3.5音頻輸出。2GB-DDR3，2個USB2.0,1個LAN，已經調試通過，固件都已經打包好。拿來就可以打板生產，包括原理圖，PCB，u-boot,kernel,rootfs。
標簽： hi3520dv400 cadence arregro
上傳時間： 2021-12-28
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
瑞芯微RK3399 軟件件設計資料 RK3399 Linux Debian軟件開發文檔資料,SDK 是基于 Linux 64bit 系統，內核基于 kernel 4.40，適用于 RK3399 挖掘機以及基于其 上所有 linux 開發產品。 支持 VPU 硬解碼、GPU 3D、QT 等功能。具體功能調試和接口說明
上傳時間： 2022-01-29
上傳用戶：
瑞芯微RK3399 軟硬件資料包括3款硬件Cadence原理圖PCB文件，硬件設計文檔，LINIUX軟件開發文檔i資料硬件文檔主要介紹RK3399處理器硬件設計的要點及注意事項，旨在幫助RK客戶縮短產品的設計周期、提高產品的設計穩定性及降低故障率。請客戶參考本指南的要求進行硬件設計，同時盡量使用RK發布的相關核心模板。 SDK 是基于 Linux 64bit 系統，內核基于 kernel 4.40，適用于 RK3399 挖掘機以及基于其 上所有 linux 開發產品。 支持 VPU 硬解碼、GPU 3D、QT 等功能。具體功能調試和接口說明，請閱讀工程目錄 docs/目錄下文檔。
上傳時間： 2022-01-29
上傳用戶：
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