There have been many developments in the field of power electronics since the publication of the second edition, almost five years ago. Devices have become bigger and better - bigger silicon die, and current and voltage ratings. However, semiconductor devices have also become smaller and better, integrated circuit devices, that is. And the marriage of low power integrated circuit tecnology and high power semiconductors has resulted in benefit to both fields.
標(biāo)簽： Electronics Handbook Edition Power
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
Radio frequency identification (RFID) is a type of automatic identification systems which has gained popularity in recent years for being fast and reliable in keeping track of the individual objects. In RFID systems, contactless object identification is achieved using radio signals without the need for physical contact as the case with other existing identification technologies such as barcodes. Therefore, a huge number of items can be identified in a short amount of time with high reliability and low cost which makes the RFID technology very attractive for a wide range of applications such as supply chain management, e-health, monitoring humans, pets, animals, and many other objects, toll control, and electrical tagging. Furthermore, RFID technology eliminates the human error and reduces the total cost of the products.
上傳時(shí)間： 2020-06-08
上傳用戶：shancjb
Although state of the art in many typical machine learning tasks, deep learning algorithmsareverycostly interms ofenergyconsumption,duetotheirlargeamount of required computations and huge model sizes. Because of this, deep learning applications on battery-constrained wearables have only been possible through wireless connections with a resourceful cloud. This setup has several drawbacks. First, there are privacy concerns. Cloud computing requires users to share their raw data—images, video, locations, speech—with a remote system. Most users are not willing to do this. Second, the cloud-setup requires users to be connected all the time, which is unfeasible given current cellular coverage. Furthermore, real-time applications require low latency connections, which cannot be guaranteed using the current communication infrastructure. Finally, wireless connections are very inefficient—requiringtoo much energyper transferredbit for real-time data transfer on energy-constrained platforms.
標(biāo)簽： Embedded_Deep_Learning Algorithms
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
)Armature windings of the electric motor for NO.2 deck cargo winch found low insulation. Windings re-winded,painted and baked dry. (2) NO.1 main air compressor failed to build up pressure.The machine disassembled, cleaned and inspected. The discharge valve plate found broken. The valve palte renewed and running trials tested after being reassembled.
標(biāo)簽： 答案
上傳時(shí)間： 2020-07-14
上傳用戶：
This design uses Common-Emitter Amplifier (Class A) with 2N3904 Bipolar Junction Transistor. Use “Voltage Divider Biasing” to reduce the effects of varying β (= ic / ib) (by holding the Base voltage constant) Base Voltage (Vb) = Vcc * [R2 / (R1 + R2)] Use Coupling Capacitors to separate the AC signals from the DC biasing voltage (which only pass AC signals and block any DC component). Use Bypass Capacitor to maintain the Q-point stability. To determine the value of each component, first set Q-point close to the center position of the load line. (RL is the resistance of the speaker.)
標(biāo)簽： 音頻放大器設(shè)計(jì) 電路圖 英文
上傳時(shí)間： 2020-11-27
上傳用戶：
1.關(guān)于等長第一次聽到“繞等長工程師”這個(gè)稱號的時(shí)候，我和我的小伙伴們都驚呆了。每次在研討會(huì)提起這個(gè)名詞，很多人也都是會(huì)心一笑。 不知道從什么時(shí)候起，繞等長成了一種時(shí)尚，也成了PCB設(shè)計(jì)工程師心中揮不去的痛。需要等長設(shè)計(jì)的總線越來越多，等長的規(guī)則越來越嚴(yán)格。5mil已經(jīng)不能滿足大家的目標(biāo)了，精益求精的工程師們開始挑戰(zhàn)1mil，0.5mil……還聽過100%等長，沒有誤差的要求。 為什么我們這么喜歡等長？打開PCB設(shè)計(jì)文件，如果沒有看到精心設(shè)計(jì)的等長線，大家心中第一反應(yīng)應(yīng)該是鄙視，居然連等長都沒做。也有過在賽格買主板或者顯卡的經(jīng)驗(yàn)，拿起板子先看看電容的設(shè)計(jì)，然后再看看繞線，如果沒有繞線或者繞線設(shè)計(jì)不美觀，直接就Pass換另一個(gè)牌子。或許在我們的心中，等長做的好，是優(yōu)秀PCB設(shè)計(jì)的一個(gè)體現(xiàn)。 做過一個(gè)非正規(guī)的統(tǒng)計(jì)（不過一博每年上萬款PCB設(shè)計(jì)，我們的采樣基本上也可以算做大數(shù)據(jù)了），稍微復(fù)雜一點(diǎn)的高速板子，繞等長要占據(jù)總設(shè)計(jì)時(shí)間的20%~30%。如果等長規(guī)則更嚴(yán)格，或者流程控制不好，做了等長之后再反復(fù)修改，這個(gè)時(shí)間還會(huì)更多。
標(biāo)簽： pcb
上傳時(shí)間： 2021-11-11
上傳用戶：
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
標(biāo)簽： 隔離
上傳時(shí)間： 2021-11-24
上傳用戶：kingwide
基于FPGA設(shè)計(jì)的字符VGA LCD顯示實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進(jìn)制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來顯示到 VGA 上，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時(shí)間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計(jì)的vga顯示測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標(biāo)簽： fpga vga顯示 verilog quartus
上傳時(shí)間： 2021-12-19
上傳用戶：kingwide
高通(Qualcomm)藍(lán)牙芯片QCC5151_硬件設(shè)計(jì)詳細(xì)指導(dǎo)書（官方內(nèi)部培訓(xùn)手冊）共52頁其內(nèi)容是針對硬件設(shè)計(jì)、部分重要元器件選擇(ESD，F(xiàn)ilter）及走線注意事項(xiàng)的詳細(xì)說明。2 Power management 2.1 SMPS 2.1.1 Components specification 2.1.2 Input power supply selection 2.1.3 Minimize SMPS EMI emissions 2.1.4 Internal LDOs and digital core decoupling 2.1.5 Powering external components 2.2 Charger 2.2.1 Charger connections.2.2.2 General charger operation2.2.3 Temperature measurement during charging 2.3 SYS_CTRL 3 Bluetooth radio3.1 RF PSU component choice 3.2 RF band-pass filter3.3 Layout (天線 走線的注意事項(xiàng))4 Audio4.1 Audio bypass capacitors 4.2 Earphone speaker output4.3 Line/Mic input 4.4 Headphone output optimizition5 LED pads 5.1 LED driver 5.2 Digital/Button input 5.3 Analog input5.4 Disabled 6 Reset pin (Reset#)7 QSPIinterface 8 USB interfaces 8.1 USB device port8.1.1 USB connections8.1.2 Layout notes8.1.3 USB charger detection
標(biāo)簽： qualcomm 藍(lán)牙芯片 qcc5151
上傳時(shí)間： 2022-01-24
上傳用戶：XuVshu
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