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max-plusII

  • 16位A/D轉(zhuǎn)換程序

    16位A/D轉(zhuǎn)換程序,使用MAX+PLUS2做的,用狀態(tài)機(jī)做的,但不夠完善,望大家見諒

    標(biāo)簽: 轉(zhuǎn)換 程序

    上傳時(shí)間: 2016-07-23

    上傳用戶:趙云興

  • The task of clustering Web sessions is to group Web sessions based on similarity and consists of max

    The task of clustering Web sessions is to group Web sessions based on similarity and consists of maximizing the intra- group similarity while minimizing the inter-group similarity. The first and foremost question needed to be considered in clustering W b sessions is how to measure the similarity between Web sessions.However.there are many shortcomings in traditiona1 measurements.This paper introduces a new method for measuring similarities between Web pages that takes into account not only the URL but also the viewing time of the visited web page.Yhen we give a new method to measure the similarity of Web sessions using sequence alignment and the similarity of W eb page access in detail Experiments have proved that our method is valid and e幣cient.

    標(biāo)簽: sessions clustering similarity Web

    上傳時(shí)間: 2014-01-11

    上傳用戶:songrui

  • 中山大學(xué)編譯原理課程的一個(gè)實(shí)驗(yàn)

    中山大學(xué)編譯原理課程的一個(gè)實(shí)驗(yàn),根據(jù)OPP(算符優(yōu)先)做的一個(gè)表達(dá)式計(jì)算器。 內(nèi)有實(shí)驗(yàn)的設(shè)計(jì)文檔。 實(shí)驗(yàn)要求支持sin,cos,max,min,power,mod,boolean,?:,等運(yùn)算。 這個(gè)代碼可以為學(xué)習(xí)編譯原理的同學(xué)參考。

    標(biāo)簽: 大學(xué) 編譯原理 實(shí)驗(yàn)

    上傳時(shí)間: 2014-01-27

    上傳用戶:PresidentHuang

  • 用prim算法實(shí)驗(yàn)最小生成樹 本程序中用到函數(shù)adjg( )

    用prim算法實(shí)驗(yàn)最小生成樹 本程序中用到函數(shù)adjg( ),此函數(shù)作用是通過接受輸入的點(diǎn)數(shù)和邊數(shù),建立無向圖。函數(shù)prg( )用于計(jì)算并輸出無向圖的鄰接矩陣。函數(shù)prim( )則用PRIM算法來尋找無向圖的最小生成樹 定義了兩個(gè)數(shù)組lowcost[max],closest[max],若頂點(diǎn)k加入U(xiǎn)中,則令lowcost[k]=0。 定義二維數(shù)組g[ ][ ]來建立無向圖的鄰接矩陣。

    標(biāo)簽: prim adjg 算法 實(shí)驗(yàn)

    上傳時(shí)間: 2016-10-07

    上傳用戶:tonyshao

  • // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial //

    // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined

    標(biāo)簽: Description Behavorial wb_master Filename

    上傳時(shí)間: 2014-07-11

    上傳用戶:zhanditian

  • The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co

    The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.

    標(biāo)簽: bus bidirectional primarily designed

    上傳時(shí)間: 2013-12-11

    上傳用戶:jeffery

  • 采用Altera公司的FPGA芯片

    采用Altera公司的FPGA芯片,在MAX+plus II軟件平臺(tái)上實(shí)現(xiàn)多路HDLC電路

    標(biāo)簽: Altera FPGA 芯片

    上傳時(shí)間: 2016-11-13

    上傳用戶:zhyiroy

  • 設(shè)計(jì)一個(gè)能進(jìn)行時(shí)、分、秒計(jì)時(shí)的十二小時(shí)制或二十四小時(shí)制的數(shù)字鐘

    設(shè)計(jì)一個(gè)能進(jìn)行時(shí)、分、秒計(jì)時(shí)的十二小時(shí)制或二十四小時(shí)制的數(shù)字鐘,并具有定時(shí)與鬧鐘功能,能在設(shè)定的時(shí)間發(fā)出鬧鈴音,能非常方便地對(duì)小時(shí)、分鐘和秒進(jìn)行手動(dòng)調(diào)節(jié)以校準(zhǔn)時(shí)間,每逢整點(diǎn),產(chǎn)生報(bào)時(shí)音報(bào)時(shí)。 實(shí)驗(yàn)平臺(tái): 1. 一臺(tái)PC機(jī); 2. MAX+PLUSII10.1。 Verilog HDL語言實(shí)現(xiàn),還有完整的實(shí)驗(yàn)報(bào)告

    標(biāo)簽: 計(jì)時(shí) 數(shù)字

    上傳時(shí)間: 2013-12-09

    上傳用戶:hphh

  • 這是我用Delphi和Matlab寫的一個(gè)程序

    這是我用Delphi和Matlab寫的一個(gè)程序,可以生成立體圖像(3DS Max 腳本)、將平面圖像立體化、基本矩陣計(jì)算、極線校正。作者保留所有權(quán)利。請(qǐng)勿用于商業(yè)用途。歡迎大家對(duì)它進(jìn)行完善。

    標(biāo)簽: Delphi Matlab 程序

    上傳時(shí)間: 2016-11-27

    上傳用戶:dapangxie

  • function [U,center,result,w,obj_fcn]= fenlei(data) [data_n,in_n] = size(data) m= 2 % Exponent fo

    function [U,center,result,w,obj_fcn]= fenlei(data) [data_n,in_n] = size(data) m= 2 % Exponent for U max_iter = 100 % Max. iteration min_impro =1e-5 % Min. improvement c=3 [center, U, obj_fcn] = fcm(data, c) for i=1:max_iter if F(U)>0.98 break else w_new=eye(in_n,in_n) center1=sum(center)/c a=center1(1)./center1 deta=center-center1(ones(c,1),:) w=sqrt(sum(deta.^2)).*a for j=1:in_n w_new(j,j)=w(j) end data1=data*w_new [center, U, obj_fcn] = fcm(data1, c) center=center./w(ones(c,1),:) obj_fcn=obj_fcn/sum(w.^2) end end display(i) result=zeros(1,data_n) U_=max(U) for i=1:data_n for j=1:c if U(j,i)==U_(i) result(i)=j continue end end end

    標(biāo)簽: data function Exponent obj_fcn

    上傳時(shí)間: 2013-12-18

    上傳用戶:ynzfm

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