controller for sending serial data at different speeds
標(biāo)簽： controller different sending serial
上傳時間： 2014-01-06
上傳用戶：woshiayin
parallel output controller
標(biāo)簽： controller parallel output
上傳時間： 2013-12-31
上傳用戶：hanli8870
The EM6125 is a bit map controller and driver for full dot matrix
標(biāo)簽： controller driver matrix 6125
上傳時間： 2014-01-13
上傳用戶：aappkkee
The EM6125 is a bit map controller and driver for full dot matrix
標(biāo)簽： controller driver matrix 6125
上傳時間： 2013-11-30
上傳用戶：liansi
The EM6125 is a bit map controller and driver for full dot matrix
標(biāo)簽： controller driver matrix 6125
上傳時間： 2017-07-20
上傳用戶：liuchee
uclinux及應(yīng)用開發(fā) 8.1 linux介紹 8.2 µ Clinux簡介 8.3 µ Clinux中的應(yīng)用程序開發(fā) 8.4 如何構(gòu)造嵌入式linux系統(tǒng) 8.5 實驗理論部分
標(biāo)簽： Clinux linux micro uclinux
上傳時間： 2014-01-08
上傳用戶：時代電子小智
CD PLAYER IDE CONTROLLER BY MCS51
標(biāo)簽： CONTROLLER PLAYER IDE MCS
上傳時間： 2017-07-23
上傳用戶：h886166
DE2-70 ltm timing Controller
標(biāo)簽： Controller timing ltm DE
上傳時間： 2014-01-16
上傳用戶：王慶才
The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been researched. The function module, state machine of digital DC/DC controller and high resolution DPWM with Sigma- Delta dither has been introduced. They are verified by experiments on a 20 W, 300 KHz non-isolated synchronous buck converters.
標(biāo)簽： Converters controller optimized Digital
上傳時間： 2013-12-31
上傳用戶：tzl1975
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field Programmable Gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2v2000ft896-4. The main idea is to design a nonlinear geometric controller which synchronizes a slave Lorenz system to a master system and then implement them into the FPGA.
標(biāo)簽： synchronization implementation controller geometric
上傳時間： 2013-12-17
上傳用戶：3到15
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