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The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of GeneralPurpose parallel Input/Output (GPIO) expansion with interrupt and reset forI2C-bus/SMBus applications and was developed to enhance the NXP Semiconductorsfamily of I2C-bus I/O expanders. I/O expanders provide a simple solution when additionalI/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
標(biāo)簽：
9539
PCA
9539R
C-bu
上傳時間：
2013-11-10
上傳用戶：ewtrwrtwe
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The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
標(biāo)簽：
C-bus
9555
SMBu
PCA
上傳時間：
2013-11-13
上傳用戶：fredguo
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The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
標(biāo)簽：
C-bus
SMBus
reset
port
上傳時間：
2014-01-18
上傳用戶：bs2005
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Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
標(biāo)簽：
Adding
Serial
SRAM
32
上傳時間：
2013-10-14
上傳用戶：cxl274287265
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The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anoutput port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
標(biāo)簽：
SMBus
Port
bit
and
上傳時間：
2013-11-09
上傳用戶：liulinshan2010
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The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
標(biāo)簽：
87C576
微控制器
編程
上傳時間：
2013-10-21
上傳用戶：xiaozhiqban
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（Portmon is an application that lets you monitor serial and parallel activity on your local system, or any computer on the network that you can reach via TCP/IP. It is the most powerful tool available for tracking down port-related configuration problems and analyzing application port usage.）
標(biāo)簽：
監(jiān)視
串口
并口
軟件
上傳時間：
2013-11-07
上傳用戶：1412904892
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
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本應(yīng)用指南講述一種實(shí)用的 MicroBlaze™ 系統(tǒng)，用于在非易失性 Platform Flash PROM 中存儲軟件代碼、用戶數(shù)據(jù)和配置數(shù)據(jù)，以簡化系統(tǒng)設(shè)計(jì)和降低成本。另外，本應(yīng)用指南還介紹一種可移植的硬件設(shè)計(jì)、一個軟件設(shè)計(jì)以及在實(shí)現(xiàn)流程中使用的其他腳本實(shí)用工具。
簡介許多 FPGA 設(shè)計(jì)都集成了使用 MicroBlaze 和 PowerPC™ 處理器的軟件嵌入式系統(tǒng)，這些設(shè)計(jì)同時使用外部易失性存儲器來執(zhí)行軟件代碼。使用易失性存儲器的系統(tǒng)還必須包含一個非易失性器件，用來在斷電期間存儲軟件代碼。大多數(shù) FPGA 系統(tǒng)都在電路板上使用 Platform FlashPROM (在本文中稱作 PROM)，用于在上電時加載 FPGA 配置數(shù)據(jù)。另外，許多應(yīng)用還可能使用其他非易失性器件(如 SPI Flash、parallel Flash 或 PIC)來保存 MAC 地址等少量用戶數(shù)據(jù)，因此導(dǎo)致系統(tǒng)電路板上存在大量非易失性器件。
標(biāo)簽：
MicroBlaze
Platform
Flash
XAPP
上傳時間：
2013-10-13
上傳用戶：hakim
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為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。
Abstract:
In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽：
QDPSK
CPLD
調(diào)制解調(diào)
電路設(shè)計(jì)
上傳時間：
2014-01-13
上傳用戶：qoovoop
