Zinc is an object oriented, platform independent, framework for designing
graphical user interfaces (GUIs) for cross platform applications. Zinc is scalable
and customizable. It provides a full-featured toolkit for the creation of GUIs and
event-driven applications.
基于Windows CE的嵌入式開發研究
Research of Embedded Development Based on Windows CE
【摘要】 近年來基于嵌入式系統的數字化產品在全球范圍內得到了突飛猛進的發展，嵌入式技術已成為一個研究熱點和消費熱點。而Windows CE由于它的多任務、實時性、模塊化、強大的通信能力等特點，在嵌入式系統的諸多領域都有了廣泛的應用。本文首先探討了嵌入式系統的特點，分類，前景，然后對各種嵌入式操作系統和Windows CE的特點及開發工具進行分析比較，接著介紹一個我們在Microsoft Windows CE 5.0環境下基于eBoxII開發的智能家居安防保全系統eDog。eDog 可以通過攝像頭將采集到的實時視頻圖像進行運動檢測，當發現有運動產生時，通過撥打電話等多種方式自動向用戶發出警報，同時將實時捕獲的圖像上傳到ftp 服務器。文章的最后詳細闡述了eDog的圖像采集模塊，運動圖像檢測模塊，圖像壓縮模塊，FTP上傳模塊的實現過程，并對我們所提出的運動檢測算法，視頻捕捉算法等做了詳細的說明。
There are many different (and often confusing) terms associated
with clock-based devices. This application note attempts
to clarify these terms, and hence serves as a comprehensive
reference on clock terminology. This application note can be
divided into two sections. The first section describes and distinguishes
between various clock sources available today.
The second section defines and distinguishes between various
parameters used to describe clocks. This section also provides methods of measuring some of these parameters.
Jitter is extremely important in systems using PLL-based
clock drivers. The effects of jitter range from not having any
effect on system operation to rendering the system completely
non-functional. This application note provides the reader
with a clear understanding of jitter in high-speed systems. It
introduces the reader to various kinds of jitter in high-speed
systems, their causes and their effects, and methods of reducing
jitter. This application note will concentrate on jitter in PLL-based frequency synthesizers.
Cypress Semiconductor makes a variety of PLL-based clock
generators. This application note provides a set of recommendations
to optimize usage of Cypress clock devices in a
system. The application note begins with recommended termination
techniques for clock generators. Subsequently, power
supply filtering and bypassing is discussed. Finally, the application
note provides some recommendations on board
layout.
