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single-chip

  • Make and answer phone calls Detect tone and pulse digit from the phone line Capture Caller ID

    Make and answer phone calls Detect tone and pulse digit from the phone line Capture Caller ID Support blind transfer, single-step transfer/conference, consultation transfer/conference, hold, unhold. Control of the local phone handset, microphone and speaker of the modem Send and receive faxes Play and record on the phone line or sound card Play music in background mode Silence detection VU Meter Wave sound editor that allows your end-users to edit their own sound files. Voice recognition and voice synthesis. Full control over the serial port device ZModem file transfer utility File compression and encryption utility

    標(biāo)簽: phone and Capture Detect

    上傳時(shí)間: 2013-11-30

    上傳用戶:水中浮云

  • Avalon Interface Specification,The Avalon interface specification is designed to accommodate periphe

    Avalon Interface Specification,The Avalon interface specification is designed to accommodate peripheral development for the system-on-a-programmable-chip (SOPC) environment. The specification provides peripheral designers with a basis for describing the address-based read/write interface found on master and slave peripherals, such as microprocessors, memory, UART, timer, etc.

    標(biāo)簽: Avalon Specification specification accommodate

    上傳時(shí)間: 2014-03-06

    上傳用戶:pompey

  • An AHB system is made of masters slaves and interconnections. A general approach to include all poss

    An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.

    標(biāo)簽: interconnections approach general include

    上傳時(shí)間: 2015-12-12

    上傳用戶:lyy1234

  • 一個(gè)verilog語言描寫的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard mem

    一個(gè)verilog語言描寫的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.兩種方式,包含testbench

    標(biāo)簽: using Fifo registers declared

    上傳時(shí)間: 2015-12-15

    上傳用戶:Avoid98

  • MPEG TS Utils application provides the user with a visual representation of the multiplexed stream s

    MPEG TS Utils application provides the user with a visual representation of the multiplexed stream structure of MPEG-2 Transport Streams (ISO/IEC 13818-1). The application allows the user to investigate the basic transport stream packets with their fields. The application also allows the user to manipulate with transport streams by filtering specified PIDs and exporting to file, demultiplexing to PES and ES streams, converting multi-program TS to single-program TS.

    標(biāo)簽: representation application multiplexed the

    上傳時(shí)間: 2015-12-15

    上傳用戶:小鵬

  • this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu

    this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.

    標(biāo)簽: implementation include quartus source

    上傳時(shí)間: 2013-12-25

    上傳用戶:壞壞的華仔

  • x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片

    x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片,本程序采用標(biāo)準(zhǔn)的C51程序編寫。- X5045 is a belt serial E2PROM CPU monitoring chip, this procedure uses the standard the C51 programming

    標(biāo)簽: E2PROM x5045 CPU 串行

    上傳時(shí)間: 2013-12-22

    上傳用戶:miaochun888

  • x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片

    x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片,本程序采用標(biāo)準(zhǔn)的C51程序編寫。- X5045 is a belt serial E2PROM CPU monitoring chip, this procedure uses the standard the C51 programming

    標(biāo)簽: E2PROM x5045 CPU 串行

    上傳時(shí)間: 2015-12-24

    上傳用戶:nanshan

  • x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片

    x5045是一個(gè)帶串行E2PROM的CPU監(jiān)控芯片,本程序采用標(biāo)準(zhǔn)的C51程序編寫。- X5045 is a belt serial E2PROM CPU monitoring chip, this procedure uses the standard the C51 programming

    標(biāo)簽: E2PROM x5045 CPU 串行

    上傳時(shí)間: 2013-12-05

    上傳用戶:as275944189

  • The Original USB 2.0 specification released on April 27, 2000 Errata to the USB 2.0 specification

    The Original USB 2.0 specification released on April 27, 2000 Errata to the USB 2.0 specification as of December 7, 2000 Mini-B connector Engineering Change Notice to the USB 2.0 specification. Pull-up/pull-down Resistors Engineering Change Notice to the USB 2.0 specification. Errata to the USB 2.0 specification as of May 28, 2002 Interface Association Descriptor Engineering Change Notice to the USB 2.0 specification. Rounded Chamfer Engineering Change Notice to the USB 2.0 specification as of October 8, 2003 Unicode Engineering Change Notice to the USB 2.0 specification as of February 21, 2005 Inter-Chip USB Supplement Revision 1.0 as of March 13, 2006 Revision 1.3 of the USB On-The-Go Supplement as of December 5, 2006 Revision 1.01 of the Micro-USB Cables and Connectors Specification as of April 4, 2007 USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification as of July 16, 2007.

    標(biāo)簽: specification 2.0 USB Original

    上傳時(shí)間: 2013-12-31

    上傳用戶:familiarsmile

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