This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2014-12-05
上傳用戶：qazxsw
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-02
上傳用戶：18862121743
The Videotransmit class is a simple wrapper that can be programmed to take video input from a source of your choice and transmit the video to a destination computer or network in JPEG format.
標(biāo)簽： Videotransmit programmed wrapper simple
上傳時(shí)間： 2014-01-06
上傳用戶：zhuyibin
The audiotransmit class is a simple wrapper that can be programmed to take audio input from a source of your choice and transmit the audio to a destination computer
標(biāo)簽： audiotransmit programmed wrapper simple
上傳時(shí)間： 2013-12-16
上傳用戶：sjyy1001
nRF24E1編程下載板是我們自行開(kāi)發(fā)的簡(jiǎn)易無(wú)線通信模塊nRF24E1的在線下載板，使用方便。 nRF24E1編程下載板源程序包括上位機(jī)程序、單片機(jī)固件程序和nRF24E1內(nèi)51核控制程序， 分別存放在“上位機(jī)程序”、“AT89S52”和“nRF24E1”三個(gè)文件夾內(nèi)。 “上位機(jī)程序”內(nèi)有應(yīng)用軟件download.exe。 “AT89S52”內(nèi)有單片機(jī)固件源程序download.c，可以直接編譯連接生成下載文件，下載到目標(biāo)單片機(jī)AT89S52中。 “nRF24E1”內(nèi)有控制nRF24E1工作的源程序，分別是： 24E1.c:典型控制應(yīng)用； putchar.c:nRF24E1串行通信源程序； transmit.c:nRF24E1無(wú)線發(fā)送源程序； receive.c:nRF24E1無(wú)線接收源程序； “Temperature”：nRF24E1控制DS18B20溫度采集并無(wú)線發(fā)送源程序。
上傳時(shí)間： 2015-05-07
上傳用戶：songyue1991
In this report we provide an overview of several closely related methods developed during the last few yers, to smooth, denoise, edit, compress, transmit, and animate very large polygonal models.
標(biāo)簽： developed overview provide closely
上傳時(shí)間： 2013-12-16
上傳用戶：ippler8
nRF24E1編程下載板是我們自行開(kāi)發(fā)的簡(jiǎn)易無(wú)線通信模塊nRF24E1的在線下載板，使用方便。 nRF24E1編程下載板源程序包括上位機(jī)程序、單片機(jī)固件程序和nRF24E1內(nèi)51核控制程序， 分別存放在“上位機(jī)程序”、“AT89S52”和“nRF24E1”三個(gè)文件夾內(nèi)。 “上位機(jī)程序”內(nèi)有應(yīng)用軟件download.exe。 “AT89S52”內(nèi)有單片機(jī)固件源程序download.c，可以直接編譯連接生成下載文件，下載到目標(biāo)單片機(jī)AT89S52中。 “nRF24E1”內(nèi)有控制nRF24E1工作的源程序，分別是： 24E1.c:典型控制應(yīng)用； putchar.c:nRF24E1串行通信源程序； transmit.c:nRF24E1無(wú)線發(fā)送源程序； receive.c:nRF24E1無(wú)線接收源程序； “Temperature”：nRF24E1控制DS18B20溫度采集并無(wú)線發(fā)送源程序。
上傳時(shí)間： 2013-12-02
上傳用戶：jackgao
nRF24E1編程下載板是我們自行開(kāi)發(fā)的簡(jiǎn)易無(wú)線通信模塊nRF24E1的在線下載板，使用方便。 nRF24E1編程下載板源程序包括上位機(jī)程序、單片機(jī)固件程序和nRF24E1內(nèi)51核控制程序， 分別存放在“上位機(jī)程序”、“AT89S52”和“nRF24E1”三個(gè)文件夾內(nèi)。 “上位機(jī)程序”內(nèi)有應(yīng)用軟件download.exe。 “AT89S52”內(nèi)有單片機(jī)固件源程序download.c，可以直接編譯連接生成下載文件，下載到目標(biāo)單片機(jī)AT89S52中。 “nRF24E1”內(nèi)有控制nRF24E1工作的源程序，分別是： 24E1.c:典型控制應(yīng)用； putchar.c:nRF24E1串行通信源程序； transmit.c:nRF24E1無(wú)線發(fā)送源程序； receive.c:nRF24E1無(wú)線接收源程序； “Temperature”：nRF24E1控制DS18B20溫度采集并無(wú)線發(fā)送源程序。
上傳時(shí)間： 2013-12-02
上傳用戶：wqxstar
This example provides a description of how to set a communication with the bxCAN in loopback mode: - transmit and receive a standard data frame by polling at 100Kbit/S - transmit and receive an extended data frame with interrupt at 500Kbit/S - lit some LEDs depending of the program succeed or not
標(biāo)簽： communication description provides loopback
上傳時(shí)間： 2016-04-24
上傳用戶：frank1234
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