VHDL實現SPI功能源代碼
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.
樣板 B 樹 ( B - tree )
規則 :
(1) 每個節點內元素個數在 [MIN,2*MIN] 之間, 但根節點元素個數為 [1,2*MIN]
(2) 節點內元素由小排到大, 元素不重複
(3) 每個節點內的指標個數為元素個數加一
(4) 第 i 個指標所指向的子節點內的所有元素值皆小於父節點的第 i 個元素
(5) B 樹內的所有末端節點深度一樣
