基于fpga的多功能數字鐘,時分秒顯示,整點報時,可設置時間段不報時,開發平臺quartus ii,語言是verilog
資源簡介:My thesis entitled \"fpga digital clock,\" immature, to enlighten
上傳時間: 2013-08-31
上傳用戶:smallfish
資源簡介:digital clock in Assembly 我的一個大學滿分VHDL作品,數字石英鐘的模擬程序。
上傳時間: 2014-01-25
上傳用戶:hullow
資源簡介:My thesis entitled "fpga digital clock," immature, to enlighten
上傳時間: 2014-01-02
上傳用戶:hxy200501
資源簡介:digital clock!看了就知道了!很不錯的東西!可以幫助你省下不少精力!
上傳時間: 2014-11-08
上傳用戶:dbs012280
資源簡介:it is a digital clock
上傳時間: 2015-12-18
上傳用戶:teddysha
資源簡介:digital clock Source using ATmega8515 and 7Segment
上傳時間: 2014-01-24
上傳用戶:王慶才
資源簡介:This document gives a project with title digital clock using labview.
上傳時間: 2017-03-20
上傳用戶:風之驕子
資源簡介:many application on kit SP-3: VGA, digital clock, counter, interface PS2....
上傳時間: 2017-04-17
上傳用戶:talenthn
資源簡介:use grapcic Dos C pain digital clock
上傳時間: 2017-06-09
上傳用戶:xymbian
資源簡介:digital clock and thermometer pic16f84
上傳時間: 2014-01-24
上傳用戶:skfreeman
資源簡介:digital clock using 8051 timer for atmel at89c52 or At89s52
上傳時間: 2017-07-16
上傳用戶:xymbian
資源簡介:digital clock arm sample code using for beginer
上傳時間: 2017-07-19
上傳用戶:邶刖
資源簡介:Programm that represents digital clock
上傳時間: 2013-12-31
上傳用戶:liglechongchong
資源簡介:digital clock Upload!
上傳時間: 2017-08-19
上傳用戶:小鵬
資源簡介:This is the source code of a digital clock implemented using Atmel 8 bit AVR Controller(ATMega16). To fully understand it look at the hardware implementation shown in attached photo(pdf).
上傳時間: 2014-08-18
上傳用戶:moshushi0009
資源簡介:Java clock is a FREE Java applet used to display a clock on your Web pages. You can display either analog or digital clock. The full source code of this applet is also available (visit my home page to download it). You may use this applet o...
上傳時間: 2014-01-12
上傳用戶:woshiayin
資源簡介:本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘,突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點,并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后,可應用于實際的數字鐘顯示中...
上傳時間: 2013-11-10
上傳用戶:hz07104032
資源簡介:DDR SDRAM控制器的VHDL源代碼,含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The digital clock M...
上傳時間: 2014-11-01
上傳用戶:l254587896
資源簡介:C++ Algorithms for digital Signal Processing 第4章 濾波器程序
上傳時間: 2013-08-01
上傳用戶:eeworm
資源簡介:·[時鐘書籍]digital clocks for Synchronization and Communications
上傳時間: 2013-05-24
上傳用戶:tgeyangjh
資源簡介:·[測試書籍]ESSENTIALS OF ELECTRONIC TESTING FOR digital, MEMORY AND MIXED-SIGNAL VLSI CIRCUITS?
上傳時間: 2013-07-21
上傳用戶:euroford
資源簡介:·Verilog?HDL:?A?Guide?to?digital?Design?and??
上傳時間: 2013-04-24
上傳用戶:誰偷了我的麥兜
資源簡介:·Stanford&IBM牛人經典之作 -? digital Control of Dynamic SystemsEditorial ReviewsProduct DescriptionThis well-respected, market-leading text discusses the use of digital computers in the real-time co
上傳時間: 2013-07-31
上傳用戶:cuiyashuo
資源簡介:digital Down Converter Design based on FPGA.
上傳時間: 2013-08-13
上傳用戶:CSUSheep
資源簡介:直接數字頻率合成(Direct digital Fraquency Synthesis,即DDFS,一般簡稱DDS)是從相位概念出發直接合成所需要波形的一種新的頻率合成技術。
上傳時間: 2013-08-27
上傳用戶:wpt
資源簡介:Fpga Implementation Of digital Timing Recovery In Software Radio Receiver
上傳時間: 2013-09-05
上傳用戶:panpanpan
資源簡介:? In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to...
上傳時間: 2013-11-22
上傳用戶:han_zh
資源簡介:Introduce High-Speed digital System Design.
上傳時間: 2013-10-20
上傳用戶:gps6888
資源簡介:Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying...
上傳時間: 2013-10-25
上傳用戶:banyou
資源簡介:? This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the ph...
上傳時間: 2013-11-04
上傳用戶:life840315