基于Verilog HDL設(shè)計(jì)的多功能數(shù)字鐘 - 免費(fèi)下載
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本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過(guò)Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過(guò)下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中。
關(guān)鍵詞：Verilog HDL；硬件描述語(yǔ)言；FPGA
Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip.
Keywords: Verilog HDL；hardware description language；FPGA
關(guān)鍵詞：Verilog HDL；硬件描述語(yǔ)言；FPGA
Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip.
Keywords: Verilog HDL；hardware description language；FPGA
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