-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
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--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
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-- Revision History :
-----------------------------------------------------------------------
-- Ver  | Author    | Mod. Date | Changes Made:
-----------------------------------------------------------------------
-- 0.1  | kam       | 9/3/99    | birth
-- 1.0  | kam       | ------    | Release
-----------------------------------------------------------------------


-- This is the top level module for a synchronous DRAM controller.  It 
-- includes a register value, a state machine, and a signal output module.


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sd_top is
  port (sdram_cs_l:     in   std_logic;                      -- sdram chip select 1
        wr_l:           in   std_logic;                      -- write strobe
        sdram_en:       in   std_logic;                      -- sdram enable
        term_l:         in   std_logic;                      -- cycle terminate
        clk:            in   std_logic;                      -- sdram clock 
        rst_l:          in   std_logic;                      -- reset signal
        byte_en:        in   std_logic_vector(3 downto 0);   -- byte enables
        add:            in   std_logic_vector(24 downto 0);  -- address bus
        sd_cke:         out  std_logic;                      -- sdram clock enable
        sd_ba:          out  std_logic_vector(1 downto 0);   -- sdram ban address
        sd_cs0_l:       out  std_logic;                      -- sdram chip select 0
        sd_cs1_l:       out  std_logic;                      -- sdram chip select 1
        sd_ras_l:       out  std_logic;                      -- sdram row address
        sd_cas_l:       out  std_logic;                      -- sdram column address
        sd_we_l:        out  std_logic;                      -- sdram write enable
        sd_add:         out  std_logic_vector(11 downto 0); -- sdram address
        sd_dqm:         out  std_logic_vector(3 downto 0);   -- sdram data qual mask
        ack_l:          out  std_logic;                      -- sdram cycle acknowledge
        sdram_setup:    inout  std_logic);                    -- sdram setup completed

--        clk:            in   std_logic;                      -- sdram clock 
--        rst_l:          in   std_logic;                      -- reset signal
--        sdram_en:       in   std_logic;                      -- sdram enable
--        wr_l:           in   std_logic;                      -- write strobe
--        sdram_cs_l:     in   std_logic;                      -- sdram chip select 1
--        term_l:         in   std_logic;                      -- cycle terminate
--        byte_en:        in   std_logic_vector(3 downto 0);   -- byte enables
--        add:            in   std_logic_vector(24 downto 0);  -- address bus
--        sd_cs0_l:       out  std_logic;                      -- sdram chip select 0
--        sd_cs1_l:       out  std_logic;                      -- sdram chip select 1
--        sd_ras_l:       out  std_logic;                      -- sdram row address
--        sd_cas_l:       out  std_logic;                      -- sdram column address
--        sd_we_l:        out  std_logic;                      -- sdram write enable
--        sd_cke:         out  std_logic;                      -- sdram clock enable
--        ack_l:          out  std_logic;                      -- sdram cycle acknowledge
--        sdram_setup:    inout  std_logic;                    -- sdram setup completed
--        sd_ba:          out  std_logic_vector(1 downto 0);   -- sdram ban address
--        sd_dqm:         out  std_logic_vector(3 downto 0);   -- sdram data qual mask
--        sd_add:         out  std_logic_vector(11 downto 0)); -- sdram address



end sd_top;

architecture RTL of sd_top is

  signal  sdram_mode_reg: std_logic_vector(11 downto 0);
  signal  sdram_cmnd:     std_logic_vector(1 downto 0);   
  signal  sdram_cycle:    std_logic_vector(3 downto 0);      -- type of cycle 
  signal  state_cntr:     std_logic_vector(3 downto 0);      -- command cycle bits
  signal  rfrsh_req:      std_logic;                         -- refresh clock
  signal  cmnd_cycle_req: std_logic;

  component sd_cnfg
    port ( clk:            in  std_logic;
           rst_l:          in  std_logic;
           sdram_en:       in  std_logic;
           sdram_cycle:    in  std_logic_vector(3 downto 0);
           state_cntr:     in  std_logic_vector(3 downto 0);
           sdram_mode_reg: out std_logic_vector(11 downto 0);
           sdram_cmnd:     out std_logic_vector(1 downto 0);
           cmnd_cycle_req: out  std_logic;
           sdram_setup:    out std_logic);
  end component;

     
  component sd_state
     port (sdram_cs_l:      in   std_logic;
           cmnd_cycle_req:  in   std_logic;
           rfrsh_req:       in   std_logic;
           clk:             in   std_logic;
           rst_l:           in   std_logic;
           sdram_cycle:     out  std_logic_vector(3 downto 0);
           state_cntr:      out  std_logic_vector(3 downto 0));
  end component;


  component sd_rfrsh
     port (clk:         in  std_logic;
           rst_l:       in  std_logic;
           sdram_setup: in  std_logic;
           sdram_cycle: in  std_logic_vector(3 downto 0);
           rfrsh_req:   out std_logic);
  end component;


  component sd_sig
     port (clk:            in   std_logic;
           rst_l:          in   std_logic;
           sdram_cycle:    in   std_logic_vector(3 downto 0);
           state_cntr:     in   std_logic_vector(3 downto 0);
           sdram_mode_reg: in   std_logic_vector(11 downto 0);
           sdram_cmnd:     in   std_logic_vector(1 downto 0);
           add:            in   std_logic_vector(24 downto 0);
           wr_l:           in   std_logic;
           byte_en:        in   std_logic_vector(3 downto 0);
           term_l:         in   std_logic;
           sd_cs0_l:       out  std_logic;
           sd_cs1_l:       out  std_logic;
           sd_ras_l:       out  std_logic;
           sd_cas_l:       out  std_logic;
           sd_we_l:        out  std_logic;
           sd_cke:         out  std_logic;
           sd_dqm:         out  std_logic_vector(3 downto 0);
           ack_l:          out  std_logic;
           sd_add:         out  std_logic_vector(11 downto 0);
           sd_ba:          out  std_logic_vector(1 downto 0));
  end component;

  begin


  U1: sd_cnfg
    port map (sdram_en => sdram_en,
              clk => clk,
              rst_l => rst_l,
              sdram_cycle => sdram_cycle,
              state_cntr => state_cntr,
              sdram_mode_reg => sdram_mode_reg,
              sdram_cmnd => sdram_cmnd,
              cmnd_cycle_req => cmnd_cycle_req,
              sdram_setup => sdram_setup);
 
  U2: sd_state
    port map (sdram_cs_l => sdram_cs_l,
             cmnd_cycle_req  => cmnd_cycle_req,
             rfrsh_req =>rfrsh_req,
             clk => clk,
             rst_l => rst_l,
             sdram_cycle => sdram_cycle,
             state_cntr => state_cntr);

  U3: sd_rfrsh
    port map (clk => clk,
              rst_l => rst_l,
              sdram_setup => sdram_setup,
              sdram_cycle => sdram_cycle,
              rfrsh_req => rfrsh_req);

  U4: sd_sig
    port map (add => add,
              wr_l => wr_l,
              byte_en => byte_en,
              term_l => term_l,
              sdram_cycle => sdram_cycle,
              state_cntr => state_cntr,
              sdram_mode_reg => sdram_mode_reg,
              sdram_cmnd => sdram_cmnd,
              rst_l => rst_l,                 
              clk => clk,
              sd_add => sd_add,
              sd_ba => sd_ba,
              sd_cs0_l => sd_cs0_l,
              sd_cs1_l => sd_cs1_l,
              sd_ras_l => sd_ras_l,
              sd_cas_l => sd_cas_l,
              sd_we_l => sd_we_l,
              sd_cke => sd_cke,
              sd_dqm => sd_dqm,
              ack_l => ack_l);
		  
end architecture RTL;