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-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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-- Copyright (c) 2001 by Lattice Semiconductor Corporation
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-- Permission:
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--   This VHDL or Verilog source code is intended as a design reference
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-- Revision History :
-----------------------------------------------------------------------
-- Ver  | Author    | Mod. Date | Changes Made:
-----------------------------------------------------------------------
-- 0.1  | kam       | 9/3/99    | birth
-- 1.0  | kam       | ------    | Release
-----------------------------------------------------------------------

-- This is the signal module for the synchronous DRAM controller.  It 
-- monitors the output of the state machine vectors and outputs the 
-- appropriate signals at the right time.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sd_sig is
     port (add:            in   std_logic_vector(24 downto 0);
           wr_l:           in   std_logic;
           byte_en:        in   std_logic_vector(3 downto 0);
           term_l:         in   std_logic;
           sdram_cycle:    in   std_logic_vector(3 downto 0);
           state_cntr:     in   std_logic_vector(3 downto 0);
           sdram_mode_reg: in   std_logic_vector(11 downto 0);
           sdram_cmnd:     in   std_logic_vector(1 downto 0);
           rst_l:          in   std_logic;
           clk:            in   std_logic;
           sd_add:         out  std_logic_vector(11 downto 0);
           sd_ba:          out  std_logic_vector(1 downto 0);
           sd_cs0_l:       out  std_logic;
           sd_cs1_l:       out  std_logic;
           sd_ras_l:       out  std_logic;
           sd_cas_l:       out  std_logic;
           sd_we_l:        out  std_logic;
           sd_cke:         out  std_logic;
           sd_dqm:         out  std_logic_vector(3 downto 0);
           ack_l:          out  std_logic);
end sd_sig;


architecture RTL of sd_sig is

  signal term_lcatch: std_logic;
  signal term_ldly:   std_logic;
		
  begin		
  ---------------------------------------------------------------------
  -- equations
  -- this is for 32 bit wide array
  -- address bits 0-1 are not used


  sd_add_set: process(clk, rst_l,sdram_cycle, state_cntr, add, sdram_mode_reg, sdram_cmnd)
    begin
      if(rst_l = '0') then
        sd_add <= "010000000000" after 1 ns;                            -- precharge
	 elsif rising_edge(clk) then 
	   if ((sdram_cycle(1) = '1') and (state_cntr = "0000") and (sdram_cmnd = "11")) then
           sd_add <=  sdram_mode_reg after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0000")) then   -- ras time
           sd_add <= add(21 downto 10) after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0010")) then   -- cas time
           sd_add <=  "1111" & add(9 downto 2) after 1 ns;
        else
           sd_add <= "010000000000" after 1 ns;                         -- precharge
        end if;
      end if;
  end process sd_add_set;


  -- bank addresses

  bank: process(clk, rst_l,sdram_cycle, state_cntr, add, sdram_mode_reg, sdram_cmnd)
    begin
      if(rst_l = '0') then
        sd_ba <= "00" after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(2) = '1') and (state_cntr = "0000")) then     -- ras time
           sd_ba <=  add(23 downto 22) after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0010")) then  -- cas time
           sd_ba <= add(23 downto 22) after 1 ns;
        else
           sd_ba <= "00" after 1 ns;
        end if;
      end if;
  end process bank;


  -- chip select 0

  chip_select_0: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sd_cs0_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(1) = '1') and (state_cntr = "0000")) then     -- cmd cycle
           sd_cs0_l <=  '0' after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0000")) then  -- ras time
           sd_cs0_l <= add(24) after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0010")) then  -- cas time
           sd_cs0_l <= add(24) after 1 ns;
        elsif ((sdram_cycle(3) = '1' and state_cntr = "0000")) then    -- refresh time
           sd_cs0_l <= '0' after 1 ns;
        elsif ((term_lcatch = '1' and sdram_cycle(2) = '1' and add(24) = '0')) then  -- term cycle 
           sd_cs0_l <= '0' after 1 ns;
        else
           sd_cs0_l <= '1' after 1 ns;
        end if;
      end if;
  end process chip_select_0;


  -- chip select 1

  chip_select_1: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sd_cs1_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(1) = '1') and (state_cntr = "0000")) then     -- cmd cycle
          sd_cs1_l <=  '0' after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0000")) then  -- ras time
          sd_cs1_l <= not add(24) after 1 ns;
        elsif ((sdram_cycle(2) = '1') and (state_cntr = "0010")) then  -- cas time
          sd_cs1_l <= not add(24) after 1 ns;
        elsif ((sdram_cycle(3) = '1' and state_cntr = "0000")) then    -- refresh time
          sd_cs1_l <= '0' after 1 ns;
        elsif ((term_lcatch = '1' and sdram_cycle(2) = '1' and add(24) = '1')) then  -- term cycle
          sd_cs1_l <= '0' after 1 ns;
        else
          sd_cs1_l <= '1' after 1 ns;
        end if;
      end if;
  end process chip_select_1;


  -- ras

  ras: process(clk, rst_l, sdram_cycle, state_cntr)
    begin
      if(rst_l = '0') then
        sd_ras_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(1) = '1' and (state_cntr = "0000")) or     -- cmd cycle
            (sdram_cycle(2) = '1' and (state_cntr = "0000")) or     -- ras time 
            (sdram_cycle(3) = '1' and (state_cntr = "0000"))) then  -- refresh time
           sd_ras_l <= '0' after 1 ns; 
        else
           sd_ras_l <= '1' after 1 ns;
        end if;
      end if;
  end process ras;

  
  -- cas

  cas: process(clk, rst_l, sdram_cycle, state_cntr)
    begin
      if(rst_l = '0') then
        sd_cas_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(1) = '1' and (state_cntr = "0000" and sdram_cmnd(1) = '1')) or 
            (sdram_cycle(2) = '1' and (state_cntr = "0010")) or      -- cas time 
            (sdram_cycle(3) = '1' and (state_cntr = "0000"))) then   -- refresh time
           sd_cas_l <= '0' after 1 ns; 
        else
           sd_cas_l <= '1' after 1 ns;
        end if;
      end if;
  end process cas;


  -- we

  we: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sd_we_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if ((sdram_cycle(1) = '1' and state_cntr = "0000" and sdram_cmnd(0) = '1') or  -- cmd cycle 
            (sdram_cycle(2) = '1' and state_cntr = "0010" and wr_l = '0') or           -- cas cycle 
            (sdram_cycle(2) = '1' and term_lcatch = '1')) then                         -- terminate
          sd_we_l <= '0' after 1 ns; 
        else
          sd_we_l <= '1' after 1 ns;
        end if;
      end if;
  end process we;


  -- clock enable

  clock_enable: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sd_cke <= '0' after 1 ns;  
      elsif rising_edge(clk) then 
        sd_cke <= '1' after 1 ns;
      end if;
  end process clock_enable;


  -- data mask

  data_mask: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sd_dqm <= "0000" after 1 ns;  
      elsif rising_edge(clk) then 
        if (sdram_cycle(2) = '1' and state_cntr = "0010") then 
           sd_dqm <= byte_en after 1 ns; 
        elsif (state_cntr = "1010") then
           sd_dqm <= "0000" after 1 ns;
        end if;
      end if;
  end process data_mask;


  -- acknowledge  

  acknowledge: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        ack_l <= '1' after 1 ns;  
      elsif rising_edge(clk) then 
        if (sdram_cycle(2) = '1' and state_cntr = "0010" and wr_l = '0') then 
          ack_l <= '0' after 1 ns; 
          -- for cas latency 2 use state_cntr = "0011"
          -- for cas latency 3 use state_cntr = "0100"
        elsif (sdram_cycle(2) = '1' and state_cntr = "0011" and wr_l = '1') then
          ack_l <= '0' after 1 ns;
        elsif (state_cntr = "1010" and wr_l = '0') then
          ack_l <= '1' after 1 ns;
          -- change for burst size other than 8
          -- for cas latency 2 use state_cntr = "1011"
          -- for cas latency 3 use state_cntr = "1100"
        elsif (state_cntr = "1011" and wr_l = '1') then
          ack_l <= '1' after 1 ns;
          -- if the cycle terminates
        elsif (sdram_cycle(2) = '0') then
          ack_l <= '1' after 1 ns;
        end if;
      end if;
  end process acknowledge;
 

  -- terminate ldly 

  terminate_ldly: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        term_ldly <= '0' after 1 ns;  
      elsif rising_edge(clk) then 
        term_ldly <= not term_l after 1 ns;
      end if;
  end process terminate_ldly;


  -- terminate catch

  terminate_catch: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        term_lcatch <= '0' after 1 ns;  
      elsif rising_edge(clk) then
        if (term_l = '0' and term_ldly = '0') then
          term_lcatch <= '1' after 1 ns;
        else
          term_lcatch <= '0' after 1 ns;
	   end if;
	 end if;
  end process terminate_catch;

end architecture RTL;