-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
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-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
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--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
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-- Revision History :
-----------------------------------------------------------------------
-- Ver  | Author    | Mod. Date | Changes Made:
-----------------------------------------------------------------------
-- 0.1  | kam       | 9/3/99    | birth
-- 1.0  | kam       | ------    | Release
-----------------------------------------------------------------------


-- This is the refresh module for the synchronous DRAM controller.  It 
-- includes a 12 bit counter which counts clock ticks.  The counter 
-- provides a refresh request every 15.8 usec.  Select the right parameter
-- based on the input clock frequency


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sd_rfrsh is
     port (clk:         in  std_logic;
           rst_l:       in  std_logic;
           sdram_setup: in  std_logic;
           sdram_cycle: in  std_logic_vector(3 downto 0);
           rfrsh_req:   out std_logic);
end sd_rfrsh;


architecture RTL of sd_rfrsh is

  -- constants -- set count to desired clock frequency
  constant cnt_66:     integer := 1053;       -- 66 Mhz clock
  constant cnt_50:     integer := 790;        -- 50 Mhz clock
  constant cnt_40:     integer := 632;        -- 40 Mhz clock
  constant cnt_33:     integer := 526;        -- 33 Mhz clock
  constant count:      integer := cnt_66;     -- set for 66 mhz
  signal   rfrsh_cntr: std_logic_vector(10 downto 0);

				   
  begin

   refresh_counter: process (clk, rst_l)
     begin
       if (rst_l = '0') then 
           rfrsh_cntr <= "00000000000" after 1 ns;
       elsif rising_edge(clk) then
           if (sdram_setup = '1' and rfrsh_cntr /= count) then
              rfrsh_cntr <= rfrsh_cntr + "00000000001" after 1 ns;
           else
              rfrsh_cntr <= "00000000000" after 1 ns;
           end if;
       end if;
   end process refresh_counter;


   refresh_request: process (clk, rst_l)
     begin
       if (rst_l = '0') then
          rfrsh_req <= '0' after 1 ns;
       elsif rising_edge(clk) then
          if (rfrsh_cntr = count) then
             rfrsh_req <= '1' after 1 ns; 
          elsif (sdram_cycle(3) = '1') then
             rfrsh_req <= '0' after 1 ns;
          end if;
       end if;
   end process refresh_request;

end architecture RTL;