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-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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-- Copyright (c) 2001 by Lattice Semiconductor Corporation
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-- Permission:
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--   Lattice Semiconductor grants permission to use this code for use
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--   use of this code, including the selling or duplication of any
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-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
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-- Revision History :
-----------------------------------------------------------------------
-- Ver  | Author    | Mod. Date | Changes Made:
-----------------------------------------------------------------------
-- 0.1  | kam       | 9/3/99    | birth
-- 1.0  | kam       | ------    | Release
-----------------------------------------------------------------------

-- This module provides an alternative to having an internal register to
-- load the sdram command mode values and to initiate the sdram startup
-- procedure.  Upon receiving the sdram_enable signal, which is assumed 
-- to be asynchronous to the clock, the state machine starts initiating 3
-- commands to the sdrams.  The first will be a precharge, the second will
-- be an auto refresh, the last will be the load mode register command.
-- After performing these threee commands, the sdram will be functional.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sd_cnfg is
     port (
           sdram_en:       in  std_logic;
           clk:            in  std_logic;
           rst_l:          in  std_logic;
           sdram_cycle:    in  std_logic_vector(3 downto 0);
           state_cntr:     in  std_logic_vector(3 downto 0);
           sdram_mode_reg: out std_logic_vector(11 downto 0);
           sdram_cmnd:     out std_logic_vector(1 downto 0);
           cmnd_cycle_req: out  std_logic;
           sdram_setup:    out std_logic);
end sd_cnfg;


architecture RTL of sd_cnfg is

  -- write mode set to single or programmed burst length -- mode bit[9]
  constant prog_brst: std_logic := '0';
  constant single:    std_logic := '1';

  -- cas latency set to 2 or 3 -- mode bits[6:4]
  constant cas_lat_2:      std_logic_vector(2 downto 0) := "010";
  constant cas_lat_3:      std_logic_vector(2 downto 0) := "011";

  -- burst type sequential or interleaved -- mode bit[3]
  constant seq: std_logic := '0';
  constant int: std_logic := '1';

  -- burst length -- mode bits(2 downto 0)
  constant brst1:      std_logic_vector(2 downto 0) := "000";  -- 1
  constant brst2:      std_logic_vector(2 downto 0) := "001";  -- 2
  constant brst4:      std_logic_vector(2 downto 0) := "010";  -- 4
  constant brst8:      std_logic_vector(2 downto 0) := "011";  -- 8
  constant brstf:      std_logic_vector(2 downto 0) := "111";  -- full page

  -- state assignments
  constant idle:      std_logic_vector(3 downto 0) := "0000";
  constant precharge: std_logic_vector(3 downto 0) := "0001";
  constant nop1:      std_logic_vector(3 downto 0) := "0010";
  constant refresh1:  std_logic_vector(3 downto 0) := "0011";
  constant nop2:      std_logic_vector(3 downto 0) := "0100";
  constant refresh2:  std_logic_vector(3 downto 0) := "0101";
  constant nop3:      std_logic_vector(3 downto 0) := "0110";
  constant load_mode: std_logic_vector(3 downto 0) := "0111";
  constant all_done:  std_logic_vector(3 downto 0) := "1000";

  signal  sdram_en1: std_logic;
  signal  sdram_en2: std_logic;	                       -- enable sync'd twice
  signal  state: std_logic_vector(3 downto 0);            -- state bits
  signal  sdram_mode_regs: std_logic_vector(11 downto 0); -- mode register

  begin

  ---------------------------------------------------------------------
  -- sdram mode register assignment
  -- change values to whatever you need

  sdram_mode_regs(11 downto 10) <= "00";       -- reserved
  sdram_mode_regs(9)            <= prog_brst;  -- write mode
  sdram_mode_regs(8 downto 7)   <= "00";       -- reserved
  sdram_mode_regs(6 downto 4)   <= cas_lat_2;  -- cas latency 2 clocks
  sdram_mode_regs(3)            <= seq;        -- sequential access
  sdram_mode_regs(2 downto 0)   <= brst8;      -- burst of 8
  sdram_mode_reg <= sdram_mode_regs;
  -----------------------------------------------------------------------
  -- synchronize enable

  sdram_enable: process(clk, rst_l)
    begin
      if(rst_l = '0') then
        sdram_en1 <= '0' after 1 ns;
        sdram_en2 <= '0' after 1 ns;
      elsif rising_edge(clk) then
        sdram_en1 <= sdram_en after 1 ns;
        sdram_en2 <= sdram_en1 after 1 ns;
      end if;
  end process sdram_enable;
			
  -- ---------------------------------------------------------------------
  -- state machine

  state_machine: process (clk, rst_l)
    begin
      if(rst_l = '0') then
        state <= idle after 1 ns;
        sdram_cmnd <= "00" after 1 ns;
        cmnd_cycle_req <= '0' after 1 ns;
        sdram_setup <= '0' after 1 ns;
      elsif rising_edge(clk) then
         case state is
            when idle => if(sdram_en2 = '1') then
                            state          <= precharge after 1 ns;
                            sdram_cmnd     <= "01" after 1 ns;
                            cmnd_cycle_req <= '1' after 1 ns;
                            sdram_setup    <= '0' after 1 ns;
                         end if;

            when precharge => if(sdram_cycle(1) = '1' and state_cntr(3) = '1') then
                                state          <= nop1 after 1 ns;
                                sdram_cmnd     <= "00" after 1 ns;
                                cmnd_cycle_req <= '0' after 1 ns;
                                sdram_setup    <= '0' after 1 ns;
                              end if;

            when nop1 => state <= refresh1 after 1 ns;
                           sdram_cmnd     <= "10" after 1 ns;
                           cmnd_cycle_req <= '1' after 1 ns;
                           sdram_setup    <= '0' after 1 ns;

            when refresh1 => if(sdram_cycle(1) = '1' and state_cntr(3) = '1') then
                               state          <= nop2 after 1 ns;
                               sdram_cmnd     <= "00" after 1 ns;
                               cmnd_cycle_req <= '0' after 1 ns;
                               sdram_setup    <= '0' after 1 ns;
                             end if;

            when nop2 => state <= refresh2 after 1 ns;
                           sdram_cmnd     <= "10" after 1 ns;
                           cmnd_cycle_req <= '1' after 1 ns;
                           sdram_setup    <= '0' after 1 ns;

            when refresh2 => if(sdram_cycle(1) = '1' and state_cntr(3) = '1') then
                               state          <= nop3 after 1 ns;
                               sdram_cmnd     <= "00" after 1 ns;
                               cmnd_cycle_req <= '0' after 1 ns;
                               sdram_setup    <= '0' after 1 ns;
                             end if;

            when nop3 => state <= load_mode after 1 ns;
                           sdram_cmnd     <= "11" after 1 ns;
                           cmnd_cycle_req <= '1' after 1 ns;
                           sdram_setup    <= '0' after 1 ns;

            when load_mode => if(sdram_cycle(1) = '1' and state_cntr(2) = '1') then
                                state          <= all_done after 1 ns;
                                sdram_cmnd     <= "00" after 1 ns;
                                cmnd_cycle_req <= '0' after 1 ns;
                                sdram_setup    <= '1' after 1 ns;
                              end if;

            when all_done => state <= all_done after 1 ns;
                               sdram_cmnd     <= "00" after 1 ns;
                               cmnd_cycle_req <= '0' after 1 ns;
                               sdram_setup    <= '1' after 1 ns;

            when others => state <= idle after 1 ns; 
                             sdram_cmnd     <= "00" after 1 ns;
                             cmnd_cycle_req <= '0' after 1 ns;
                             sdram_setup    <= '0' after 1 ns;
         end case;
      end if;
  end process state_machine;
end architecture RTL;