?? prefixandorcendaround.vhd
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--------------------------------------------------------------------------------- Title : Parallel-prefix AND-OR structure for end-around carry-- Project : VHDL Library of Arithmetic Units--------------------------------------------------------------------------------- File : PrefixAndOrCendaround.vhd-- Author : Reto Zimmermann <zimmi@iis.ee.ethz.ch>-- Company : Integrated Systems Laboratory, ETH Zurich-- Date : 1997/11/04--------------------------------------------------------------------------------- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich--------------------------------------------------------------------------------- Description :-- Prefix AND-OR structure with-- - fast carry-in (CI)-- - carry-out (CO) independent of carry-in (for end-around carry adders)-------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library arith_lib;use arith_lib.arith_lib.all;use arith_lib.arith_utils.all;-------------------------------------------------------------------------------entity PrefixAndOrCendaround is generic (width : integer := 8; -- word width speed : integer := 2); -- performance parameter port (GI, PI : in std_logic_vector(width-1 downto 0); -- gen./prop. in CI : in std_logic; -- carry in GO, PO : out std_logic_vector(width-1 downto 0); -- gen./prop. out CO : out std_logic); -- carry outend PrefixAndOrCendaround;-------------------------------------------------------------------------------architecture Structural of PrefixAndOrCendaround is signal GT, PT : std_logic_vector(width-1 downto 0); -- gen./prop. tempbegin -- normal prefix calculation prefix : PrefixAndOr generic map (width, speed) port map (GI, PI, GT, PT); -- carry-out CO <= GT(width-1); -- additional prefix calculation level for fast carry-in GO <= GT or (PT and (width-1 downto 0 => CI)); PO <= PT;end Structural;-------------------------------------------------------------------------------
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