--------------------------------------------------------------------------------- Title       : Parallel-prefix AND-OR structure with fast carry-in-- Project     : VHDL Library of Arithmetic Units--------------------------------------------------------------------------------- File        : PrefixAndOrCfast.vhd-- Author      : Reto Zimmermann  <zimmi@iis.ee.ethz.ch>-- Company     : Integrated Systems Laboratory, ETH Zurich-- Date        : 1997/11/04--------------------------------------------------------------------------------- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich--------------------------------------------------------------------------------- Description :-- Prefix AND-OR structure with--   - fast carry-in (CI)-------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library arith_lib;use arith_lib.arith_lib.all;use arith_lib.arith_utils.all;-------------------------------------------------------------------------------entity PrefixAndOrCfast is  generic (width : positive := 8;	-- word width	   speed : speedType := fast);	-- performance parameter  port (GI, PI : in std_logic_vector(width-1 downto 0);  -- gen./prop. in        CI : in std_logic;  		-- carry in	GO, PO : out std_logic_vector(width-1 downto 0));  -- gen./prop. outend PrefixAndOrCfast;-------------------------------------------------------------------------------architecture Structural of PrefixAndOrCfast is   signal CIT : std_logic_vector(width-1 downto 0);  -- carry in temp  signal GT, PT : std_logic_vector(width-1 downto 0);  -- gen./prop. tempbegin  -- normal prefix calculation  prefix : PrefixAndOr    generic map (width, speed)    port map (GI, PI, GT, PT);  -- additional prefix calculation level for fast carry-in  CIT <= (others => CI);  GO <= GT or (PT and CIT);end Structural;-------------------------------------------------------------------------------