--------------------------------------------------------------------------------- Title       : Parallel-prefix decrementer with carry-in, carry-out-- Project     : VHDL Library of Arithmetic Units--------------------------------------------------------------------------------- File        : DecC.vhd-- Author      : Reto Zimmermann  <zimmi@iis.ee.ethz.ch>-- Company     : Integrated Systems Laboratory, ETH Zurich-- Date        : 1997/11/04--------------------------------------------------------------------------------- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich--------------------------------------------------------------------------------- Description :-- Decrementer using parallel-prefix propagate-lookahead logic with:--   - carry-in (CI)--   - carry-out (CO)-------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library synergy;  use synergy.signed_arith.all;library arith_lib;use arith_lib.arith_lib.all;-------------------------------------------------------------------------------entity DecC is  generic (width : positive := 8;  	-- word width	   speed : speedType := fast);  -- performance parameter  port (A : in std_logic_vector(width-1 downto 0);  -- operand        CI : in std_logic;  		-- carry in	Z : out std_logic_vector(width-1 downto 0);  -- result        CO : out std_logic);  		-- carry outend DecC;-------------------------------------------------------------------------------architecture Behavioral of DecC is  signal Auns, CIuns, Zuns : unsigned(width downto 0);  -- unsignedbegin  -- type conversion: std_logic_vector -> unsigned  Auns <= conv_unsigned(A, width+1);  CIuns <= (0 => CI, others => '0');  -- decrement  Zuns <= Auns - CIuns;  -- type conversion: unsigned -> std_logic_vector  Z <= std_logic_vector(Zuns(width-1 downto 0));  CO <= Zuns(width);end Behavioral;-------------------------------------------------------------------------------architecture Structural of DecC is   signal AI : std_logic_vector(width downto 0);  -- A inverted  signal PO : std_logic_vector(width downto 0);  -- prefix propagate outbegin  -- invert A for decrement  AI <= (not A) & CI;    -- calculate prefix output propagate signal  prefix : PrefixAnd    generic map (width+1, speed)    port map (AI, PO);  -- calculate result and carry-out bits  Z <= A xor PO(width-1 downto 0);  CO <= PO(width);end Structural;-------------------------------------------------------------------------------