library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FIFOxy is
	generic(wide:integer:=8);
    Port ( Clk : in std_logic;
           Rst : in std_logic;
           WR : in std_logic;
           RD : in std_logic;
           WrPtrClr : in std_logic;
           Wrinc : in std_logic;
           RdPtrClr : in std_logic;
           Rdinc : in std_logic;
           Data_in : in std_logic_vector(8 downto 0);
           Data_out : out std_logic_vector(8 downto 0));
end FIFOxy;

architecture Arch_FIFO of FIFOxy is
	type fifo_array is array(7 downto 0) of std_logic_vector(8 downto 0);
	signal fifo : fifo_array;
	signal en : std_logic_vector(7 downto 0);
	signal dMuxout : std_logic_vector(8 downto 0);
	signal wrptr : std_logic_vector(2 downto 0);
	signal rdptr : std_logic_vector(2 downto 0);
begin

	reg_array: process(rst,clk)
	begin
		if rst='1' then
			for i in 7 downto 0 loop
				fifo(i) <= (others=>'0');
			end loop;
		elsif (clk'event and clk='1') then			
			if wr='1' then
				for i in 7 downto 0 loop			
					if en(i)='1' then
						fifo(i)<=data_in;
					else
						fifo(i)<=fifo(i);
					end if;
				end loop;
			end if;
		end if;
	end process;	
			
	read_count: process(rst,clk)
	begin
		if rst='1' then
			rdptr <= "000";
		elsif (clk'event and clk='1') then
			if rdptrclr='1' then
				rdptr <= "000";
			elsif rdinc='1' then
				rdptr <= rdptr+1;
			end if;
		end if;	
	end process;
	
	write_count: process(rst,clk)
	begin
		if rst='1' then
			wrptr <= "000";
		elsif (clk'event and clk='1') then
			if wrptrclr='1' then
				wrptr <= "000";
			elsif wrinc='1' then
				wrptr <= wrptr+1;
			end if;
		end if;	
	end process;
	
	dMux: process(rdptr)
	begin			
		WITH rdptr SELECT
			dMuxout <= fifo(0) when "000",
				fifo(1) when "001",
				fifo(2) when "010",
				fifo(3) when "011",
				fifo(4) when "100",
				fifo(5) when "101",
				fifo(6) when "110",
				fifo(7) when others;			
	end process;

	tri_state: process(rd,dmuxout)
	begin
		if rd='1' then
			data_out <= dMuxout;
		else
			data_out <= (others=>'Z');
		end if;
	end process;
	
	sel: process(wrptr)
	begin		
		with wrptr select
			en <= "00000001" when "000" ,
				"00000010" when "001" ,
				"00000100" when "010" ,
				"00001000" when "011" ,
				"00010000" when "100" ,
				"00100000" when "101" ,
				"01000000" when "110" ,
				"10000000" when others ;
	end process;

end Arch_FIFO;