library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clkgen is
    port(clk:in std_logic;
         outclk_1M,
         outclk_100K,
         outclk_10K,
         outclk_1K,
         outclk_100,
         outclk_10,
         outclk_1:out std_logic);
end clkgen;

architecture clkgen of clkgen is
component div10
    port(clk:in std_logic;
           outclk:out std_logic);
end component;
signal ca_1M,
          ca_100K,
          ca_10K,
          ca_1K,
          ca_100,
          ca_10,
          ca_1:std_logic;
begin
    clk1M:div10 port map(clk=>clk,outclk=>ca_1M);
    clk100K:div10 port map(clk=>ca_1M,outclk=>ca_100K);
    clk10K:div10 port map(clk=>ca_100K,outclk=>ca_10K);
    clk1K:div10 port map(clk=>ca_10K,outclk=>ca_1K);
    clk100:div10 port map(clk=>ca_1K,outclk=>ca_100);
    clk10:div10 port map(clk=>ca_100,outclk=>ca_10);
    clk1:div10 port map(clk=>ca_10,outclk=>ca_1);
    outclk_1M<=ca_1M;
    outclk_100K<=ca_100K;
    outclk_10K<=ca_10K;
    outclk_1K<=ca_1K;
    outclk_100<=ca_100;
    outclk_10<=ca_10;
    outclk_1<=ca_1;

end clkgen;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div10 is
     port(clk:in std_logic;
               outclk: out std_logic);
end div10;

architecture div10 of div10 is  
       signal qs:std_logic_vector(3 downto 0);
       signal ca:std_logic;
       begin
       process(clk)
       begin
            if(clk'event and clk='1' ) then
                if(qs="1001") then
                       qs<="0000";
                       ca<='1';
               else
                      qs<=qs+'1';
                      ca<='0';
       end if;
     end if;
     end process;

outclk<=ca;
end div10;

library ieee;
use ieee.std_logic_1164.all;

entity traffic is
    port(clkin:in std_logic;
            clrn:in std_logic;
            hg:out std_logic;
            hy:out std_logic;
            hr:out std_logic;
            vg:out std_logic;
            vy:out std_logic;
            vr:out std_logic);
end traffic;

architecture traffic of traffic is
type light_states is(HGVR,
                              HYVR,
                              VGHR,
                              VYHR);
signal qs_lights:std_logic_vector(5 downto 0);
signal current_state:light_states;
signal next_state:light_states;

begin 
      process(clkin,current_state,clrn)
      begin
           if(clrn='0') then  
                          next_state<=current_state;
          elsif(clkin'event and clkin='1') then 
                          current_state<=next_state;
                  case current_state is
                          when HGVR=>qs_lights<="100001";
                                    next_state<=HYVR;
                          when HYVR=>qs_lights<="010001";
                                    next_state<=VGHR;
                          when VGHR=>qs_lights<="001100";
                                    next_state<=VYHR;
                          when VYHR=>qs_lights<="001010";
                                    next_state<=HGVR;
                          when others=>qs_lights<="000000";
                                    next_state<=HGVR; 
                 end case;
          end if;
end process;

            hg<=qs_lights(5);
            hy<=qs_lights(4);
            hr<=qs_lights(3);
            vg<=qs_lights(2);
            vy<=qs_lights(1);
            vr<=qs_lights(0);
end traffic;

  
library ieee;
use ieee.std_logic_1164.all;

entity control is
    port(clk:in std_logic;
            clrn:in std_logic;
            hg:out std_logic;
            hy:out std_logic;
            hr:out std_logic;
            vg:out std_logic;
            vy:out std_logic;
            vr:out std_logic;
            LED_COM:out std_logic);
end control;

architecture control of control is
component clkgen
       port(clk:in std_logic;
                    outclk_1M,
                    outclk_100K,
                    outclk_10K,
                    outclk_1K,
                    outclk_100,
                    outclk_10,
                    outclk_1:out std_logic);
end component;

component traffic
         port(clkin:in std_logic;
                 clrn:in std_logic;
                 hg:out std_logic;
                 hy:out std_logic;
                 hr:out std_logic;
                 vg:out std_logic;
                 vy:out std_logic;
                 vr:out std_logic);
end component;

signal qs_clk1:std_logic;
begin
     u0:clkgen port map(clk=>clk,outclk_1=>qs_clk1);
     u1:traffic port map(clkin=>qs_clk1,
                                   clrn=>clrn,
                                   hg=>hg,
                                   hy=>hy,
                                   hr=>hr,
                                   vg=>vg,
                                   vy=>vy,
                                   vr=>vr);
         LED_COM<='1';
end control;