TITLE "Compact UART, Receiver Module"; 
-- Version 1.0, April 4th 1997
-- Copyright Rune Baeverrud
-- You may use or distribute this LPM function freely,
-- provided you do not remove this copyright notice.
-- You can download it from www.fpga.com.cn or www.pld.com.cn

PARAMETERS
(
  WIDTH = 8,
  MSB_FIRST = "YES",
  RX_BUFFER = "NO"
);

SUBDESIGN uart_rx
(
	SysClk	 : INPUT;
	BaudGen	 : INPUT;
	RxD		   : INPUT;
		
	D[WIDTH-1..0]	: OUTPUT;
  Sample   : OUTPUT;
  DValid	 : OUTPUT;
  DEnable  : OUTPUT
)

VARIABLE
	Ss			: MACHINE WITH STATES (idle, wait_before_sample, sample , wait_after_sample,
                                 wait_after_last_sample, wait_before_stop_bit);
	Sync[2..0]	            : DFFE;
	BitCnt[CEIL(LOG2(WIDTH+1))-1..0] : DFF;
  Shift[WIDTH-1..0] : DFF;
  EnableReg  							: SRFF;
  ValidReg                : SRFF;
  Sync_is_4							  : NODE;
  DTemp[WIDTH-1..0] : NODE;

  IF RX_BUFFER == "YES" GENERATE
    Buffer[WIDTH-1..0] : DFFE;
  END GENERATE;

BEGIN
  ASSERT (WIDTH > 1)
	REPORT "Value of WIDTH parameter (%) must be equal to or greater than 2"
    WIDTH
	SEVERITY ERROR;

  ASSERT (MSB_FIRST == "YES" OR MSB_FIRST == "NO")
	REPORT "Value of MSB_FIRST parameter (%) must be ""YES"" OR ""NO"""
    MSB_FIRST
	SEVERITY ERROR;

  ASSERT (RX_BUFFER == "YES" OR RX_BUFFER == "NO")
	REPORT "Value of RX_BUFFER parameter (%) must be ""YES"" OR ""NO"""
    RX_BUFFER
	SEVERITY ERROR;

	Ss.clk = SysClk;
	Sync[].clk = SysClk;
	BitCnt[].clk = SysClk;
  Shift[].clk = SysClk;
  EnableReg.clk = SysClk;
  ValidReg.clk = SysClk;
  
  DValid = ValidReg;
  DEnable = EnableReg;

  IF RX_BUFFER == "YES" GENERATE
    Buffer[].clk = SysClk;
  END GENERATE;


-- If Sync_is_4 is true, it is time to sample RxD
  IF Sync[] == 4 THEN
    Sync_is_4 = VCC;
  END IF;

-- Receiver state machine control
  CASE Ss IS
  	WHEN idle =>
      IF RxD THEN
        Ss = wait_before_sample;
      ELSE
        Ss = idle;
      END IF;
  	WHEN wait_before_sample =>
      IF Sync_is_4 THEN
        ValidReg.R = VCC;
        Ss = sample;
      ELSE
        Ss = wait_before_sample;
      END IF;
  	WHEN sample =>
      IF BitCnt[] == 0 THEN
        EnableReg.S = VCC;
        ValidReg.S = VCC;

  IF RX_BUFFER == "YES" GENERATE
    Buffer[].ena = VCC;
  END GENERATE;

        Ss = wait_after_last_sample;
      ELSE
        Ss = wait_after_sample;
      END IF;
  	WHEN wait_after_sample =>
      IF Sync_is_4 THEN
        Ss = wait_after_sample;
      ELSE
        Ss = wait_before_sample;
      END IF;
    WHEN wait_after_last_sample =>
      EnableReg.R = VCC;
      IF Sync_is_4 THEN
        Ss = wait_after_last_sample;
      ELSE
        Ss = wait_before_stop_bit;
      END IF;
    WHEN wait_before_stop_bit =>
      IF Sync_is_4 THEN
        Ss = idle;
      ELSE
        Ss = wait_before_stop_bit;
      END IF;  
    WHEN OTHERS =>
      Ss = idle;
  END CASE;

-- Sample synchronization counter  
  Sync[].ena = BaudGen;
  IF Ss == idle THEN
    Sync[] = 0;
  ELSE
    Sync[] = Sync[] + 1;
  END IF;

-- Keep track of number of bits received
  CASE Ss IS
    WHEN idle =>
      BitCnt[] = WIDTH;
    WHEN sample =>
      BitCnt[] = BitCnt[] - 1;
    WHEN OTHERS =>
      BitCnt[] = BitCnt[];
  END CASE;

-- Sample and shift
  IF Ss == sample THEN
    Shift[WIDTH-1..1] = Shift[WIDTH-2..0];
    Shift[0] = RxD;

    IF RX_BUFFER == "YES" GENERATE
      Buffer[WIDTH-1..1] = Shift[WIDTH-2..0];
      Buffer[0] = RxD;
    END GENERATE;
  ELSE
    Shift[] = Shift[];
  END IF;

  IF Ss == sample THEN
    Sample = VCC;
  END IF;

  IF RX_BUFFER == "YES" GENERATE
    DTemp[] = Buffer[];
  ELSE GENERATE
    DTemp[] = Shift[];
  END GENERATE;

  IF MSB_FIRST == "YES" GENERATE
    D[] = DTemp[];
  ELSE GENERATE
	  FOR each_bit IN 0 TO WIDTH-1 GENERATE
      D[WIDTH -1 -each_bit] = DTemp[each_bit];	
    END GENERATE;
  END GENERATE;

END;