TITLE "div_by_n Frequency Divider Module"; 
-- Version 2.0, January 29, 1998
-- Copyright Rune Baeverrud, 1996-1998
-- You may use or distribute this function freely,
-- provided you do not remove this copyright notice.
-- You can download this freecore from www.fpga.com.cn or www.pld.com.cn

PARAMETERS
(
  DIVISOR = 2
);

CONSTANT NUM_BITS = CEIL(LOG2(DIVISOR));
CONSTANT DIVISOR_MINUS_ONE = DIVISOR - 1;

INCLUDE "lpm_counter";
INCLUDE "lpm_compare";

SUBDESIGN div_by_n
(
  SysClk           : INPUT;
  cnt_en           : INPUT = VCC;
  sclr             : INPUT = GND;
  Every_N          : OUTPUT;
  q[NUM_BITS-1..0] : OUTPUT;
)

VARIABLE
  counter          : LPM_COUNTER WITH (LPM_WIDTH = NUM_BITS);
  max_cnt          : NODE;
  Deglitch         : DFF;

BEGIN
  ASSERT (DIVISOR > 1)
	REPORT "Value of DIVISOR parameter (%) must be equal to or greater than 2"
      DIVISOR
	SEVERITY ERROR;

  ASSERT
    REPORT "div_by_n module will operate internally using % bits."
      NUM_BITS
    SEVERITY INFO;

  max_cnt = LPM_COMPARE(DIVISOR_MINUS_ONE, counter.q[],,,)
            WITH (LPM_WIDTH = NUM_BITS,
                  ONE_INPUT_IS_CONSTANT = "YES")
            RETURNS (.aeb);
 
  counter.clock  = SysClk;
  counter.cnt_en = cnt_en;
  counter.sclr   = (max_cnt AND cnt_en) OR sclr;

  Deglitch     = max_cnt AND cnt_en;
  Deglitch.clk = SysClk;
  Every_n      = Deglitch;

  q[] = counter.q[];
END;