TITLE "DRAM Controller with Refresh (CAS before RAS) and DTACK Generation" ;
-- Version 1.1, 03.02.1998
-- Copyright Frank Rodler
-- You can download it from www.fpga.com.cn or www.pld.com.cn

PARAMETERS
(
   F_IN_MHZ = 40 ,        -- [MHz]   means F_clk is 40MHz
   RFSH_INTERVAL = 15     -- [us]    15 means: 1 refresh cycle every 15us
) ;

CONSTANT  RFSH_DIV = F_IN_MHZ * RFSH_INTERVAL;

FUNCTION div_by_n (sysclk, cnt_en, sclr)
    WITH (DIVISOR)
    RETURNS (every_n, q[(ceil(log2(divisor))) - (1)..0]);

SUBDESIGN DynRam     -- That's our interface name to the rest of the world
(
   clk        : INPUT ;       -- global clock (default: 40MHz with 60ns DRAMs)
   nWrB[3..0] : INPUT ;       -- write byte 3,2,1,0 
   nRd        : INPUT ;       -- read all bytes
   nCS        : INPUT ;       -- chip select of DRAM 
   Reset      : INPUT = GND ; -- reset tu power up state
   AS         : INPUT = VCC ; -- adress strobe

   CAS[3..0]  : OUTPUT ;  -- column select for byte groups 3,2,1,0
   RASx       : OUTPUT ;  -- row select for all byte groups
   RamWr      : OUTPUT ;  -- write line for all DRAM chips
   DTACK      : OUTPUT ;  -- data transfer acknowledge
   AdMux0     : OUTPUT ;  -- address mux 0 (for external MUX eg.: 74FCT[2]244)
   AdMux1     : OUTPUT ;  -- address mux 1 (for external MUX eg.: 74FCT[2]244)
   rc_mux     : OUTPUT ;  -- HIGH when input multiplexer should switch
   RefRun     : OUTPUT ;  -- signal that currently a refresh cycle is running
)

VARIABLE		          -- I tell the compiler what staff I want to use
   cas_[3..0] : TFF ;
   dtack_     : TFF ;
   ramwr_     : TFF ;
   Ref_pend   : TFF ;
   rc_mux     : DFF ;
   refresh_cnt : div_by_n WITH (DIVISOR = RFSH_DIV) ;

   Phase  : MACHINE OF BITS
             (RA,RA_1,RAS,hlp3,hlp2,hlp1)  WITH STATES (
   S0     = B"000000" ,   -- ILLEGAL or Power Up
   S1     = B"100000" ,   -- 20 Idle
   S2     = B"101000" ,   -- 28 RAS (for 130ns L)
   S3     = B"011001" ,   -- 19 MUX (RA)
   S4     = B"011011" ,   -- 1B CAS (on demand.)
   S6     = B"110010" ,   -- 32 DTACK on, RAS off (for >= 100ns H)
   S7     = B"100010" ,   -- 22 wait
 
   S8     = B"100100" ,   -- 24 CAS on (CAS before RAS Refr.)
   S9     = B"101100" ,   -- 2C RAS on (for 130ns L)
   S10    = B"101101" ,   -- 2D CAS off
   S11    = B"101111" ,   -- 2F    
   S12    = B"100111" ,   -- 27 RAS off
   S13    = B"100110" ) ; -- 26 


BEGIN

ASSERT (RFSH_DIV == 2)
REPORT "INFO: Refresh predivider :(%)" RFSH_DIV 
  SEVERITY INFO ;

Phase.clk = clk ;
Phase.reset = Reset ;
cas_[].clk = clk ;
dtack_.clk = clk ;
ramwr_.clk = clk ;

CASE Phase IS
  WHEN S0 =>
    cas_[].t = cas_[].q ;   -- all signals to inactiv state
    dtack_.t = dtack_.q ;
    ramwr_.t = ramwr_.q ;
    Phase = S1 ;            -- jump always to idle

  WHEN S1 =>
    IF (Ref_pend.q) THEN
      cas_[].t = !cas_[].q ;
      Phase = S8 ;
    ELSIF (!nCS) THEN       -- if nCS is LOW than start access (S2)
      Phase = S2 ;
    END IF ;

  WHEN S2 =>
    IF !(nWrB0 & nWrB1 & nWrB2 & nWrB3) THEN
      ramwr_.t = !ramwr_.q ;
    END IF ;
    Phase = S3 ;

  WHEN S3 =>
    cas_0.t = (!cas_0.q & !nWrB0 & nRd) # (!cas_0.q & nWrB0 & !nRd) ; 
    cas_1.t = (!cas_1.q & !nWrB1 & nRd) # (!cas_1.q & nWrB1 & !nRd) ; 
    cas_2.t = (!cas_2.q & !nWrB2 & nRd) # (!cas_2.q & nWrB2 & !nRd) ; 
    cas_3.t = (!cas_3.q & !nWrB3 & nRd) # (!cas_3.q & nWrB3 & !nRd) ; 
    Phase = S4 ;

   WHEN S4 =>
     dtack_.t = !dtack_.q ;      -- assert DTACK
     Phase = S6 ;

   WHEN S6 =>
     IF (ramwr_.q) THEN
       ramwr_.t = ramwr_.q ;     -- set write (DRAM) signal to inactiv
     END IF ;
     Phase = S7 ;

   WHEN S7 =>
     IF (AS & nCS) THEN          -- wait 'till processor finishes access
       Phase = S1 ;
     END IF ;

   %---------------    Refresh Cycle ------------------------------------%

   WHEN S8 =>
     Phase = S9 ;

   WHEN S9 =>
     cas_[].t = cas_[].q ;   -- all CAS to inactiv state
     Phase = S10 ;

   WHEN S10 =>
	 Phase = S11 ;

   WHEN S11 =>
     Phase = S12 ;

   WHEN S12 =>
     Phase = S13 ;

   WHEN S13 =>
     Phase = S1 ;            -- all refresh done, back to idle state

END CASE ;

-- during S6 and S7 it's allowed for CAS and DTACK to return to the inactiv state :
cas_[].clrn = !(cas_[].q & AS & nCS & ((Phase == S6) # (Phase == S7))) ;
dtack_.clrn = !(dtack_.q & AS & nCS & ((Phase == S6) # (Phase == S7))) ;

refresh_cnt.sysclk = clk ;
refresh_cnt.cnt_en = VCC ;
refresh_cnt.sclr = Reset ;
Ref_pend.clk = clk ;
Ref_pend.t = (!Ref_pend.q & refresh_cnt.every_n) # (Ref_pend.q & (Phase == S13)) ;

CAS[]  = cas_[].q ;
RASx   = RAS ;
RamWr  = ramwr_.q ;
DTACK  = dtack_.q ;
AdMux0 = RA ;
AdMux1 = RA_1 ;
RefRun = hlp3 ;

rc_mux.clk = clk ;
rc_mux.d = (Phase == S2) # (Phase == S6) ;

END ;