?? fen2.vhd
字號(hào):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FEN2 IS
PORT(
SW_B,CS:IN STD_LOGIC;
IN1,IN2,IN3:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FEN2;
ARCHITECTURE A OF FEN2 IS
SIGNAL OT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(SW_B,CS,IN1,IN2,IN3,OT)
BEGIN
IF (SW_B='0') THEN OT<=IN2;
ELSIF(SW_B='1' AND CS='0') THEN OT<=IN3;
ELSE
OT<=IN1;
END IF;
EW<=OT;
END PROCESS;
END A;
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