-- Xilinx Vhdl produced by program ngd2vhdl E.38-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w mouse.nga mouse_timesim.vhd -- Input file: mouse.nga-- Output file: mouse_timesim.vhd-- Design name: mouse-- Xilinx: d:/Xilinx-- # of Entities: 1-- Device: 2s100tq144-5-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,-- or used in any other manner other than simulation. This netlist uses simulation-- primitives which may not represent the true implementation of the device, however-- the netlist is functionally correct. Do not modify this file.-- Model for  ROC (Reset-On-Configuration) Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is  generic (InstancePath: STRING := "*";           WIDTH : Time := 100 ns);  port(O : out std_ulogic := '1') ;  attribute VITAL_LEVEL0 of ROC : entity is TRUE;end ROC;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;begin  ONE_SHOT : process  begin    if (WIDTH <= 0 ns) then       assert FALSE report       "*** Error: a positive value of WIDTH must be specified ***"       severity failure;    else       wait for WIDTH;       O <= '0';    end if;    wait;  end process ONE_SHOT;end ROC_V;-- Model for  TOC (Tristate-On-Configuration) Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is  generic (InstancePath: STRING := "*";           WIDTH : Time := 0 ns);  port(O : out std_ulogic := '0');  attribute VITAL_LEVEL0 of TOC : entity is TRUE;end TOC;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;begin  ONE_SHOT : process  begin    O <= '1';    if (WIDTH <= 0 ns) then       O <= '0';    else       wait for WIDTH;       O <= '0';    end if;    wait;  end process ONE_SHOT;end TOC_V;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity mouse is  port (    clk : in STD_LOGIC := 'X';     xsign : out STD_LOGIC;     error_no_ack : out STD_LOGIC;     ysign : out STD_LOGIC;     left_button : out STD_LOGIC;     ps2_data : inout STD_LOGIC;     reset : in STD_LOGIC := 'X';     right_button : out STD_LOGIC;     ps2_clk : inout STD_LOGIC;     x_increment : out STD_LOGIC_VECTOR ( 8 downto 0 );     y_increment : out STD_LOGIC_VECTOR ( 8 downto 0 )   );end mouse;architecture Structure of mouse is  component ROC    generic (InstancePath: STRING := "*";             WIDTH : Time := 100 ns);    port (O : out STD_ULOGIC := '1');  end component;  component TOC    generic (InstancePath: STRING := "*";             WIDTH : Time := 0 ns);    port (O : out STD_ULOGIC := '1');  end component;  signal N244 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_9 : STD_LOGIC;   signal clk_BUFGP : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_11 : STD_LOGIC;   signal N217 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_13 : STD_LOGIC;   signal Madd_n0033_inst_cy_1 : STD_LOGIC;   signal GLOBAL_LOGIC1 : STD_LOGIC;   signal GLOBAL_LOGIC0 : STD_LOGIC;   signal N393 : STD_LOGIC;   signal Madd_n0033_inst_cy_3 : STD_LOGIC;   signal N385 : STD_LOGIC;   signal N397 : STD_LOGIC;   signal N401 : STD_LOGIC;   signal N249 : STD_LOGIC;   signal m1_state_FFD2_1 : STD_LOGIC;   signal N313 : STD_LOGIC;   signal N342 : STD_LOGIC;   signal N222 : STD_LOGIC;   signal N228 : STD_LOGIC;   signal N234 : STD_LOGIC;   signal N242 : STD_LOGIC;   signal N247 : STD_LOGIC;   signal reset_IBUF : STD_LOGIC;   signal m2_state_FFD14 : STD_LOGIC;   signal m2_state_FFD3 : STD_LOGIC;   signal m2_state_FFD2 : STD_LOGIC;   signal m2_state_FFD4 : STD_LOGIC;   signal m2_state_FFD8 : STD_LOGIC;   signal N2316 : STD_LOGIC;   signal N344 : STD_LOGIC;   signal m2_state_FFD9 : STD_LOGIC;   signal N329 : STD_LOGIC;   signal N282 : STD_LOGIC;   signal m1_state_FFD1 : STD_LOGIC;   signal N271 : STD_LOGIC;   signal m1_state_FFD2_2 : STD_LOGIC;   signal m1_state_FFD2 : STD_LOGIC;   signal N2340 : STD_LOGIC;   signal m2_state_FFD10 : STD_LOGIC;   signal N319 : STD_LOGIC;   signal m2_state_FFD11 : STD_LOGIC;   signal N317 : STD_LOGIC;   signal N2310 : STD_LOGIC;   signal N2312 : STD_LOGIC;   signal N272 : STD_LOGIC;   signal m2_state_FFD12 : STD_LOGIC;   signal m2_state_FFD13 : STD_LOGIC;   signal m1_state_FFD5 : STD_LOGIC;   signal m1_state_FFD6 : STD_LOGIC;   signal m1_state_FFD4 : STD_LOGIC;   signal N2336 : STD_LOGIC;   signal m1_state_FFD3 : STD_LOGIC;   signal N258 : STD_LOGIC;   signal m2_state_FFD1 : STD_LOGIC;   signal m2_state_FFD6 : STD_LOGIC;   signal m2_state_FFD5 : STD_LOGIC;   signal y_increment_0_OBUF : STD_LOGIC;   signal y_increment_1_OBUF : STD_LOGIC;   signal y_increment_2_OBUF : STD_LOGIC;   signal y_increment_3_OBUF : STD_LOGIC;   signal y_increment_4_OBUF : STD_LOGIC;   signal y_increment_5_OBUF : STD_LOGIC;   signal y_increment_6_OBUF : STD_LOGIC;   signal y_increment_7_OBUF : STD_LOGIC;   signal x_increment_0_OBUF : STD_LOGIC;   signal m2_state_FFD7 : STD_LOGIC;   signal N210 : STD_LOGIC;   signal x_increment_2_OBUF : STD_LOGIC;   signal x_increment_3_OBUF : STD_LOGIC;   signal xsign_OBUF : STD_LOGIC;   signal ysign_OBUF : STD_LOGIC;   signal x_increment_8_OBUF : STD_LOGIC;   signal y_increment_8_OBUF : STD_LOGIC;   signal x_increment_1_OBUF : STD_LOGIC;   signal clk_BUFGP_IBUFG : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_7 : STD_LOGIC;   signal GLOBAL_LOGIC1_0 : STD_LOGIC;   signal GLOBAL_LOGIC0_0 : STD_LOGIC;   signal watchdog_timer_count_4_CYINIT : STD_LOGIC;   signal N484 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_10 : STD_LOGIC;   signal watchdog_timer_count_4_LOGIC_ZERO : STD_LOGIC;   signal watchdog_timer_count_4_CYMUXG : STD_LOGIC;   signal watchdog_timer_count_4_GROM : STD_LOGIC;   signal watchdog_timer_count_4_FROM : STD_LOGIC;   signal N486 : STD_LOGIC;   signal watchdog_timer_count_4_FFY_RST : STD_LOGIC;   signal watchdog_timer_count_4_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_4_FFX_RST : STD_LOGIC;   signal watchdog_timer_count_4_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_6_CYINIT : STD_LOGIC;   signal N417 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_12 : STD_LOGIC;   signal watchdog_timer_count_6_LOGIC_ZERO : STD_LOGIC;   signal watchdog_timer_count_6_CYMUXG : STD_LOGIC;   signal watchdog_timer_count_6_GROM : STD_LOGIC;   signal watchdog_timer_count_6_FROM : STD_LOGIC;   signal N482 : STD_LOGIC;   signal watchdog_timer_count_6_FFY_RST : STD_LOGIC;   signal watchdog_timer_count_6_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_6_FFX_RST : STD_LOGIC;   signal watchdog_timer_count_6_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_8_CYINIT : STD_LOGIC;   signal watchdog_timer_count_8_GROM : STD_LOGIC;   signal watchdog_timer_count_8_rt : STD_LOGIC;   signal N488 : STD_LOGIC;   signal watchdog_timer_count_8_FFX_RST : STD_LOGIC;   signal watchdog_timer_count_8_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N393_LOGIC_ZERO : STD_LOGIC;   signal N393_CYINIT : STD_LOGIC;   signal N393_XORG : STD_LOGIC;   signal Madd_n0033_inst_cy_0 : STD_LOGIC;   signal N393_CYMUXG : STD_LOGIC;   signal N393_GROM : STD_LOGIC;   signal Madd_n0033_inst_lut2_0 : STD_LOGIC;   signal N385_CYINIT : STD_LOGIC;   signal N385_XORG : STD_LOGIC;   signal Madd_n0033_inst_cy_2 : STD_LOGIC;   signal N385_LOGIC_ZERO : STD_LOGIC;   signal N385_CYMUXG : STD_LOGIC;   signal N385_GROM : STD_LOGIC;   signal N385_FROM : STD_LOGIC;   signal N385_XORF : STD_LOGIC;   signal N401_CYINIT : STD_LOGIC;   signal N401_XORG : STD_LOGIC;   signal Madd_n0033_inst_cy_4 : STD_LOGIC;   signal bitcount_5_rt : STD_LOGIC;   signal N401_FROM : STD_LOGIC;   signal N401_XORF : STD_LOGIC;   signal N401_LOGIC_ZERO : STD_LOGIC;   signal N313_GROM : STD_LOGIC;   signal N313_FROM : STD_LOGIC;   signal N242_GROM : STD_LOGIC;   signal N242_FROM : STD_LOGIC;   signal bitcount_1_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N391 : STD_LOGIC;   signal N395 : STD_LOGIC;   signal bitcount_1_FFY_RST : STD_LOGIC;   signal bitcount_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal bitcount_1_FFX_RST : STD_LOGIC;   signal bitcount_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal bitcount_3_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N387 : STD_LOGIC;   signal N399 : STD_LOGIC;   signal bitcount_3_FFY_RST : STD_LOGIC;   signal bitcount_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal bitcount_3_FFX_RST : STD_LOGIC;   signal bitcount_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal bitcount_5_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N403 : STD_LOGIC;   signal N251 : STD_LOGIC;   signal bitcount_5_FFY_RST : STD_LOGIC;   signal bitcount_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal bitcount_5_FFX_RST : STD_LOGIC;   signal bitcount_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD4_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N370 : STD_LOGIC;   signal N375 : STD_LOGIC;   signal m2_state_FFD4_FFY_RST : STD_LOGIC;   signal m2_state_FFD4_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD4_FFX_RST : STD_LOGIC;   signal m2_state_FFD4_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD9_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N348 : STD_LOGIC;   signal m2_state_FFD9_FROM : STD_LOGIC;   signal m2_state_FFD9_FFY_RST : STD_LOGIC;   signal m2_state_FFD9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD2_2_SRMUX_OUTPUTNOT : STD_LOGIC;   signal m1_state_FFD2_2_GROM : STD_LOGIC;   signal m1_state_FFD2_2_FFY_RST : STD_LOGIC;   signal m1_state_FFD2_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD2_2_FFX_RST : STD_LOGIC;   signal m1_state_FFD2_2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD10_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N334 : STD_LOGIC;   signal m2_state_FFD10_FROM : STD_LOGIC;   signal m2_state_FFD10_FFY_RST : STD_LOGIC;   signal m2_state_FFD10_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD11_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N325 : STD_LOGIC;   signal m2_state_FFD11_FROM : STD_LOGIC;   signal m2_state_FFD11_FFY_RST : STD_LOGIC;   signal m2_state_FFD11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD14_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N297 : STD_LOGIC;   signal N292 : STD_LOGIC;   signal m2_state_FFD14_FFY_RST : STD_LOGIC;   signal m2_state_FFD14_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD14_FFX_RST : STD_LOGIC;   signal m2_state_FFD14_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD6_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N273 : STD_LOGIC;   signal N269 : STD_LOGIC;   signal m1_state_FFD6_FFY_RST : STD_LOGIC;   signal m1_state_FFD6_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD6_FFX_RST : STD_LOGIC;   signal m1_state_FFD6_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N2336_GROM : STD_LOGIC;   signal N2336_FROM : STD_LOGIC;   signal m1_state_FFD3_SRMUX_OUTPUTNOT : STD_LOGIC;   signal m1_state_FFD3_GROM : STD_LOGIC;   signal N260 : STD_LOGIC;   signal m1_state_FFD3_FFX_RST : STD_LOGIC;   signal m1_state_FFD3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD5_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N353 : STD_LOGIC;   signal m2_state_FFD5_FFY_RST : STD_LOGIC;   signal m2_state_FFD5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD5_FFX_RST : STD_LOGIC;   signal m2_state_FFD5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_12_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_12_FFY_RST : STD_LOGIC;   signal q_12_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_12_FFX_RST : STD_LOGIC;   signal q_12_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_22_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_22_FFY_RST : STD_LOGIC;   signal q_22_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_22_FFX_RST : STD_LOGIC;   signal q_22_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_14_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_14_FFY_RST : STD_LOGIC;   signal q_14_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_14_FFX_RST : STD_LOGIC;   signal q_14_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_0_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_0_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_0_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_31_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_31_FFY_RST : STD_LOGIC;   signal q_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_24_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_24_FFY_RST : STD_LOGIC;   signal q_24_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_24_FFX_RST : STD_LOGIC;   signal q_24_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_16_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_16_FFY_RST : STD_LOGIC;   signal q_16_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_16_FFX_RST : STD_LOGIC;   signal q_16_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_1_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_1_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_1_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_32_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_32_FFY_RST : STD_LOGIC;   signal q_32_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_2_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_2_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_2_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_26_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_26_FFY_RST : STD_LOGIC;   signal q_26_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_26_FFX_RST : STD_LOGIC;   signal q_26_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_18_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_18_FFY_RST : STD_LOGIC;   signal q_18_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_18_FFX_RST : STD_LOGIC;   signal q_18_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_3_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_3_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_3_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal debounce_timer_count_0_BXMUXNOT : STD_LOGIC;   signal N264 : STD_LOGIC;   signal debounce_timer_count_0_FFY_RST : STD_LOGIC;   signal debounce_timer_count_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal debounce_timer_count_0_FFX_RST : STD_LOGIC;   signal debounce_timer_count_0_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_4_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_4_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_4_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_28_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_28_FFY_RST : STD_LOGIC;   signal q_28_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_28_FFX_RST : STD_LOGIC;   signal q_28_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_20_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_20_FFY_RST : STD_LOGIC;   signal q_20_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_20_FFX_RST : STD_LOGIC;   signal q_20_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_5_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_5_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_5_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_6_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_6_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_6_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_30_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_30_FFY_RST : STD_LOGIC;   signal q_30_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_30_FFX_RST : STD_LOGIC;   signal q_30_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_7_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_7_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_7_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal x_increment_0_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal x_increment_0_OBUF_FFY_RST : STD_LOGIC;   signal x_increment_0_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N210_GROM : STD_LOGIC;   signal N222_GROM : STD_LOGIC;   signal N222_FROM : STD_LOGIC;   signal m2_state_FFD2_LOGIC_ZERO : STD_LOGIC;   signal m2_state_FFD2_SRMUX_OUTPUTNOT : STD_LOGIC;   signal m2_state_FFD2_GROM : STD_LOGIC;   signal N364 : STD_LOGIC;   signal m2_state_FFD2_FFY_SET : STD_LOGIC;   signal m2_state_FFD2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD2_FFX_RST : STD_LOGIC;   signal m2_state_FFD2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N228_GROM : STD_LOGIC;   signal m2_state_FFD12_SRMUX_OUTPUTNOT : STD_LOGIC;   signal m2_state_FFD12_GROM : STD_LOGIC;   signal N301 : STD_LOGIC;   signal m2_state_FFD12_FFX_RST : STD_LOGIC;   signal m2_state_FFD12_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal x_increment_2_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal x_increment_2_OBUF_FFY_RST : STD_LOGIC;   signal x_increment_2_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal x_increment_3_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal x_increment_3_OBUF_FFY_RST : STD_LOGIC;   signal x_increment_3_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal xsign_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal xsign_OBUF_FFY_RST : STD_LOGIC;   signal xsign_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal ysign_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal ysign_OBUF_FFY_RST : STD_LOGIC;   signal ysign_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal x_increment_8_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal x_increment_8_OBUF_FFY_RST : STD_LOGIC;   signal x_increment_8_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal y_increment_8_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal y_increment_8_OBUF_FFY_RST : STD_LOGIC;   signal y_increment_8_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal x_increment_1_OBUF_SRMUX_OUTPUTNOT : STD_LOGIC;   signal x_increment_1_OBUF_FFY_RST : STD_LOGIC;   signal x_increment_1_OBUF_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_2_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_2_FFY_RST : STD_LOGIC;   signal q_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_2_FFX_RST : STD_LOGIC;   signal q_2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N234_GROM : STD_LOGIC;   signal N234_FROM : STD_LOGIC;   signal q_4_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_4_FFY_RST : STD_LOGIC;   signal q_4_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_4_FFX_RST : STD_LOGIC;   signal q_4_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m2_state_FFD8_SRMUX_OUTPUTNOT : STD_LOGIC;   signal m2_state_FFD8_GROM : STD_LOGIC;   signal I_m2_state_XX_FFD8_O : STD_LOGIC;   signal m2_state_FFD8_FFX_RST : STD_LOGIC;   signal m2_state_FFD8_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_6_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_6_FFY_RST : STD_LOGIC;   signal q_6_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_6_FFX_RST : STD_LOGIC;   signal q_6_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_8_SRMUX_OUTPUTNOT : STD_LOGIC;   signal q_8_FFY_RST : STD_LOGIC;   signal q_8_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_8_FFX_RST : STD_LOGIC;   signal q_8_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_10_SRMUX_OUTPUTNOT : STD_LOGIC;