signal q_10_FFY_RST : STD_LOGIC;   signal q_10_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal q_10_FFX_RST : STD_LOGIC;   signal q_10_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N2340_GROM : STD_LOGIC;   signal xsign_OD : STD_LOGIC;   signal xsign_OUTMUX : STD_LOGIC;   signal xsign_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_0_OD : STD_LOGIC;   signal x_increment_0_OUTMUX : STD_LOGIC;   signal x_increment_0_OUTBUF_GTS_TRI : STD_LOGIC;   signal error_no_ack_OD : STD_LOGIC;   signal error_no_ack_OUTMUX : STD_LOGIC;   signal error_no_ack_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_1_OD : STD_LOGIC;   signal x_increment_1_OUTMUX : STD_LOGIC;   signal x_increment_1_OUTBUF_GTS_TRI : STD_LOGIC;   signal ysign_OD : STD_LOGIC;   signal ysign_OUTMUX : STD_LOGIC;   signal ysign_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_2_OD : STD_LOGIC;   signal x_increment_2_OUTMUX : STD_LOGIC;   signal x_increment_2_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_3_OD : STD_LOGIC;   signal x_increment_3_OUTMUX : STD_LOGIC;   signal x_increment_3_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_4_OD : STD_LOGIC;   signal x_increment_4_OUTMUX : STD_LOGIC;   signal x_increment_4_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_5_OD : STD_LOGIC;   signal x_increment_5_OUTMUX : STD_LOGIC;   signal x_increment_5_OUTBUF_GTS_TRI : STD_LOGIC;   signal left_button_OD : STD_LOGIC;   signal left_button_OUTMUX : STD_LOGIC;   signal left_button_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_0_OD : STD_LOGIC;   signal y_increment_0_OUTMUX : STD_LOGIC;   signal y_increment_0_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_6_OD : STD_LOGIC;   signal x_increment_6_OUTMUX : STD_LOGIC;   signal x_increment_6_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_1_OD : STD_LOGIC;   signal y_increment_1_OUTMUX : STD_LOGIC;   signal y_increment_1_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_7_OD : STD_LOGIC;   signal x_increment_7_OUTMUX : STD_LOGIC;   signal x_increment_7_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_2_OD : STD_LOGIC;   signal y_increment_2_OUTMUX : STD_LOGIC;   signal y_increment_2_OUTBUF_GTS_TRI : STD_LOGIC;   signal x_increment_8_OD : STD_LOGIC;   signal x_increment_8_OUTMUX : STD_LOGIC;   signal x_increment_8_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_3_OD : STD_LOGIC;   signal y_increment_3_OUTMUX : STD_LOGIC;   signal y_increment_3_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_4_OD : STD_LOGIC;   signal y_increment_4_OUTMUX : STD_LOGIC;   signal y_increment_4_OUTBUF_GTS_TRI : STD_LOGIC;   signal ps2_data_IBUF : STD_LOGIC;   signal ps2_data_LOGIC_ZERO : STD_LOGIC;   signal ps2_data_OUTMUX : STD_LOGIC;   signal ps2_data_TORGTS : STD_LOGIC;   signal ps2_data_ENABLE : STD_LOGIC;   signal ps2_data_OUTBUF_GTS_AND : STD_LOGIC;   signal y_increment_5_OD : STD_LOGIC;   signal y_increment_5_OUTMUX : STD_LOGIC;   signal y_increment_5_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_6_OD : STD_LOGIC;   signal y_increment_6_OUTMUX : STD_LOGIC;   signal y_increment_6_OUTBUF_GTS_TRI : STD_LOGIC;   signal reset_IBUF_0 : STD_LOGIC;   signal y_increment_7_OD : STD_LOGIC;   signal y_increment_7_OUTMUX : STD_LOGIC;   signal y_increment_7_OUTBUF_GTS_TRI : STD_LOGIC;   signal y_increment_8_OD : STD_LOGIC;   signal y_increment_8_OUTMUX : STD_LOGIC;   signal y_increment_8_OUTBUF_GTS_TRI : STD_LOGIC;   signal right_button_OD : STD_LOGIC;   signal right_button_OUTMUX : STD_LOGIC;   signal right_button_OUTBUF_GTS_TRI : STD_LOGIC;   signal ps2_clk_IBUF : STD_LOGIC;   signal ps2_clk_LOGIC_ZERO : STD_LOGIC;   signal ps2_clk_TDATANOT : STD_LOGIC;   signal ps2_clk_OUTMUX : STD_LOGIC;   signal ps2_clk_TORGTS : STD_LOGIC;   signal ps2_clk_ENABLE : STD_LOGIC;   signal ps2_clk_OUTBUF_GTS_AND : STD_LOGIC;   signal m1_state_FFD1_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N2355 : STD_LOGIC;   signal N279 : STD_LOGIC;   signal N2357 : STD_LOGIC;   signal m1_state_FFD1_FFY_RST : STD_LOGIC;   signal m1_state_FFD1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD1_FFX_SET : STD_LOGIC;   signal m1_state_FFD1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal m1_state_FFD4_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N2346 : STD_LOGIC;   signal N287 : STD_LOGIC;   signal N2348 : STD_LOGIC;   signal m1_state_FFD4_FFX_RST : STD_LOGIC;   signal m1_state_FFD4_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N317_GROM : STD_LOGIC;   signal N317_F5MUX : STD_LOGIC;   signal N2366 : STD_LOGIC;   signal m2_state_FFD7_SRMUX_OUTPUTNOT : STD_LOGIC;   signal N2360 : STD_LOGIC;   signal N383 : STD_LOGIC;   signal N2362 : STD_LOGIC;   signal m2_state_FFD7_FFX_RST : STD_LOGIC;   signal m2_state_FFD7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal N2351 : STD_LOGIC;   signal N247_F5MUX : STD_LOGIC;   signal m1_state_FFD2_rt : STD_LOGIC;   signal watchdog_timer_count_0_LOGIC_ZERO : STD_LOGIC;   signal watchdog_timer_count_0_CYINIT : STD_LOGIC;   signal N491 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_6 : STD_LOGIC;   signal watchdog_timer_count_0_CYMUXG : STD_LOGIC;   signal watchdog_timer_count_0_GROM : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_lut2_6 : STD_LOGIC;   signal watchdog_timer_count_0_FFY_RST : STD_LOGIC;   signal watchdog_timer_count_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_0_FFX_RST : STD_LOGIC;   signal watchdog_timer_count_0_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_2_CYINIT : STD_LOGIC;   signal N489 : STD_LOGIC;   signal watchdog_timer_count_Madd_n0000_inst_cy_8 : STD_LOGIC;   signal watchdog_timer_count_2_LOGIC_ZERO : STD_LOGIC;   signal watchdog_timer_count_2_CYMUXG : STD_LOGIC;   signal watchdog_timer_count_2_GROM : STD_LOGIC;   signal watchdog_timer_count_2_FROM : STD_LOGIC;   signal N490 : STD_LOGIC;   signal watchdog_timer_count_2_FFY_RST : STD_LOGIC;   signal watchdog_timer_count_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;   signal watchdog_timer_count_2_FFX_RST : STD_LOGIC;   signal watchdog_timer_count_2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC;   signal GSR : STD_LOGIC;   signal GTS : STD_LOGIC;   signal PWR_VCC_0_FROM : STD_LOGIC;   signal VCC : STD_LOGIC;   signal GND : STD_LOGIC;   signal NlwInverterSignal_xsign_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_0_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_error_no_ack_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_1_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_ysign_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_2_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_3_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_4_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_5_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_left_button_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_0_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_6_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_1_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_7_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_2_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_x_increment_8_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_3_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_4_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_ps2_data_OUTBUF_GTS_AND_IN1 : STD_LOGIC;   signal NlwInverterSignal_y_increment_5_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_6_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_7_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_y_increment_8_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_right_button_OUTBUF_GTS_TRI_CTL : STD_LOGIC;   signal NlwInverterSignal_ps2_clk_OUTBUF_GTS_AND_IN1 : STD_LOGIC;   signal watchdog_timer_count : STD_LOGIC_VECTOR ( 8 downto 0 );   signal bitcount : STD_LOGIC_VECTOR ( 5 downto 0 );   signal debounce_timer_count : STD_LOGIC_VECTOR ( 1 downto 0 );   signal q : STD_LOGIC_VECTOR ( 32 downto 1 ); begin  watchdog_timer_count_Madd_n0000_inst_sum_11 : X_XOR2    port map (      I0 => watchdog_timer_count_Madd_n0000_inst_cy_10,      I1 => watchdog_timer_count_4_GROM,      O => N484    );  watchdog_timer_count_Madd_n0000_inst_cy_11_1 : X_MUX2    port map (      IA => watchdog_timer_count_4_LOGIC_ZERO,      IB => watchdog_timer_count_Madd_n0000_inst_cy_10,      SEL => watchdog_timer_count_4_GROM,      O => watchdog_timer_count_4_CYMUXG    );  watchdog_timer_count_4_G : X_LUT4    generic map(      INIT => X"FF00"    )    port map (      ADR0 => VCC,      ADR1 => VCC,      ADR2 => VCC,      ADR3 => watchdog_timer_count(5),      O => watchdog_timer_count_4_GROM    );  watchdog_timer_count_4_F : X_LUT4    generic map(      INIT => X"CCCC"    )    port map (      ADR0 => VCC,      ADR1 => watchdog_timer_count(4),      ADR2 => VCC,      ADR3 => VCC,      O => watchdog_timer_count_4_FROM    );  watchdog_timer_count_Madd_n0000_inst_sum_10 : X_XOR2    port map (      I0 => watchdog_timer_count_4_CYINIT,      I1 => watchdog_timer_count_4_FROM,      O => N486    );  watchdog_timer_count_Madd_n0000_inst_cy_10_2 : X_MUX2    port map (      IA => watchdog_timer_count_4_LOGIC_ZERO,      IB => watchdog_timer_count_4_CYINIT,      SEL => watchdog_timer_count_4_FROM,      O => watchdog_timer_count_Madd_n0000_inst_cy_10    );  watchdog_timer_count_4_CYINIT_3 : X_BUF    port map (      I => watchdog_timer_count_Madd_n0000_inst_cy_9,      O => watchdog_timer_count_4_CYINIT    );  watchdog_timer_count_4_LOGIC_ZERO_4 : X_ZERO    port map (      O => watchdog_timer_count_4_LOGIC_ZERO    );  watchdog_timer_count_4_COUTUSED : X_BUF    port map (      I => watchdog_timer_count_4_CYMUXG,      O => watchdog_timer_count_Madd_n0000_inst_cy_11    );  watchdog_timer_count_5 : X_FF    port map (      I => N484,      CE => N244,      CLK => clk_BUFGP,      SET => GND,      RST => watchdog_timer_count_4_FFY_ASYNC_FF_GSR_OR,      O => watchdog_timer_count(5)    );  watchdog_timer_count_4_FFY_RSTOR : X_BUF    port map (      I => N217,      O => watchdog_timer_count_4_FFY_RST    );  watchdog_timer_count_4_FFY_ASYNC_FF_GSR_OR_5 : X_OR2    port map (      I0 => watchdog_timer_count_4_FFY_RST,      I1 => GSR,      O => watchdog_timer_count_4_FFY_ASYNC_FF_GSR_OR    );  watchdog_timer_count_4 : X_FF    port map (      I => N486,      CE => N244,      CLK => clk_BUFGP,      SET => GND,      RST => watchdog_timer_count_4_FFX_ASYNC_FF_GSR_OR,      O => watchdog_timer_count(4)    );  watchdog_timer_count_4_FFX_RSTOR : X_BUF    port map (      I => N217,      O => watchdog_timer_count_4_FFX_RST    );  watchdog_timer_count_4_FFX_ASYNC_FF_GSR_OR_6 : X_OR2    port map (      I0 => watchdog_timer_count_4_FFX_RST,      I1 => GSR,      O => watchdog_timer_count_4_FFX_ASYNC_FF_GSR_OR    );  watchdog_timer_count_Madd_n0000_inst_sum_13 : X_XOR2    port map (      I0 => watchdog_timer_count_Madd_n0000_inst_cy_12,      I1 => watchdog_timer_count_6_GROM,      O => N417    );  watchdog_timer_count_Madd_n0000_inst_cy_13_7 : X_MUX2    port map (      IA => watchdog_timer_count_6_LOGIC_ZERO,      IB => watchdog_timer_count_Madd_n0000_inst_cy_12,      SEL => watchdog_timer_count_6_GROM,      O => watchdog_timer_count_6_CYMUXG    );  watchdog_timer_count_6_G : X_LUT4    generic map(      INIT => X"FF00"    )    port map (      ADR0 => VCC,      ADR1 => VCC,      ADR2 => VCC,      ADR3 => watchdog_timer_count(7),      O => watchdog_timer_count_6_GROM    );  watchdog_timer_count_6_F : X_LUT4    generic map(      INIT => X"CCCC"    )    port map (      ADR0 => VCC,      ADR1 => watchdog_timer_count(6),      ADR2 => VCC,      ADR3 => VCC,      O => watchdog_timer_count_6_FROM    );  watchdog_timer_count_Madd_n0000_inst_sum_12 : X_XOR2    port map (      I0 => watchdog_timer_count_6_CYINIT,      I1 => watchdog_timer_count_6_FROM,      O => N482    );  watchdog_timer_count_Madd_n0000_inst_cy_12_8 : X_MUX2    port map (      IA => watchdog_timer_count_6_LOGIC_ZERO,      IB => watchdog_timer_count_6_CYINIT,      SEL => watchdog_timer_count_6_FROM,      O => watchdog_timer_count_Madd_n0000_inst_cy_12    );  watchdog_timer_count_6_CYINIT_9 : X_BUF    port map (      I => watchdog_timer_count_Madd_n0000_inst_cy_11,      O => watchdog_timer_count_6_CYINIT    );  watchdog_timer_count_6_LOGIC_ZERO_10 : X_ZERO    port map (      O => watchdog_timer_count_6_LOGIC_ZERO    );  watchdog_timer_count_6_COUTUSED : X_BUF    port map (      I => watchdog_timer_count_6_CYMUXG,      O => watchdog_timer_count_Madd_n0000_inst_cy_13    );  watchdog_timer_count_7 : X_FF    port map (      I => N417,      CE => N244,      CLK => clk_BUFGP,      SET => GND,      RST => watchdog_timer_count_6_FFY_ASYNC_FF_GSR_OR,      O => watchdog_timer_count(7)    );  watchdog_timer_count_6_FFY_RSTOR : X_BUF    port map (      I => N217,      O => watchdog_timer_count_6_FFY_RST    );  watchdog_timer_count_6_FFY_ASYNC_FF_GSR_OR_11 : X_OR2    port map (      I0 => watchdog_timer_count_6_FFY_RST,      I1 => GSR,      O => watchdog_timer_count_6_FFY_ASYNC_FF_GSR_OR    );  watchdog_timer_count_6 : X_FF    port map (      I => N482,      CE => N244,      CLK => clk_BUFGP,      SET => GND,      RST => watchdog_timer_count_6_FFX_ASYNC_FF_GSR_OR,      O => watchdog_timer_count(6)    );  watchdog_timer_count_6_FFX_RSTOR : X_BUF    port map (      I => N217,      O => watchdog_timer_count_6_FFX_RST    );  watchdog_timer_count_6_FFX_ASYNC_FF_GSR_OR_12 : X_OR2    port map (      I0 => watchdog_timer_count_6_FFX_RST,      I1 => GSR,      O => watchdog_timer_count_6_FFX_ASYNC_FF_GSR_OR    );  watchdog_timer_count_8_G : X_LUT4    generic map(      INIT => X"FFFF"    )    port map (      ADR0 => VCC,      ADR1 => VCC,      ADR2 => VCC,      ADR3 => VCC,      O => watchdog_timer_count_8_GROM    );  watchdog_timer_count_8_rt_13 : X_LUT4    generic map(      INIT => X"CCCC"    )    port map (      ADR0 => VCC,      ADR1 => watchdog_timer_count(8),      ADR2 => VCC,      ADR3 => VCC,      O => watchdog_timer_count_8_rt    );  watchdog_timer_count_Madd_n0000_inst_sum_14 : X_XOR2    port map (      I0 => watchdog_timer_count_8_CYINIT,      I1 => watchdog_timer_count_8_rt,      O => N488    );  watchdog_timer_count_8_CYINIT_14 : X_BUF    port map (      I => watchdog_timer_count_Madd_n0000_inst_cy_13,      O => watchdog_timer_count_8_CYINIT    );  watchdog_timer_count_8_YUSED : X_BUF    port map (      I => watchdog_timer_count_8_GROM,      O => GLOBAL_LOGIC1_0    );  watchdog_timer_count_8 : X_FF    port map (      I => N488,      CE => N244,      CLK => clk_BUFGP,      SET => GND,      RST => watchdog_timer_count_8_FFX_ASYNC_FF_GSR_OR,      O => watchdog_timer_count(8)    );  watchdog_timer_count_8_FFX_RSTOR : X_BUF    port map (      I => N217,      O => watchdog_timer_count_8_FFX_RST    );  watchdog_timer_count_8_FFX_ASYNC_FF_GSR_OR_15 : X_OR2    port map (      I0 => watchdog_timer_count_8_FFX_RST,      I1 => GSR,      O => watchdog_timer_count_8_FFX_ASYNC_FF_GSR_OR    );  Madd_n0033_inst_sum_1 : X_XOR2    port map (      I0 => Madd_n0033_inst_cy_0,      I1 => N393_GROM,      O => N393_XORG    );  Madd_n0033_inst_cy_1_16 : X_MUX2    port map (      IA => GLOBAL_LOGIC0,      IB => Madd_n0033_inst_cy_0,      SEL => N393_GROM,      O => N393_CYMUXG    );  N393_G : X_LUT4    generic map(      INIT => X"FF00"    )    port map (      ADR0 => GLOBAL_LOGIC0,      ADR1 => VCC,      ADR2 => VCC,      ADR3 => bitcount(1),      O => N393_GROM    );  Madd_n0033_inst_lut2_0_17 : X_LUT4    generic map(      INIT => X"3333"    )    port map (      ADR0 => GLOBAL_LOGIC1_0,      ADR1 => bitcount(0),      ADR2 => VCC,      ADR3 => VCC,