?? icon.edn
字號(hào):
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 9 23 11 38 52)
(author "Xilinx, Inc.")
(program "ChipScope Core Generator" (version "v4.1i"))))
(comment "**********************************
Component Name: icon
Device Family: Virtex/VirtexE/Spartan2
Port count: 1
Disable JTAG global clock buffer: false
Enable external trigger in: false
Enable external trigger out: false
**********************************")
(comment "This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of design files
limited to Xilinx devices or technologies. Use with non-Xilinx devices or
technologies is expressly prohibited and immediately terminates your license.
Xilinx products are not intended for use in life support appliances, devices,
or systems. Use in such applications are expressly prohibited.
Copyright (C) 2001, Xilinx, Inc. All Rights Reserved.")
(comment "Core parameters: ")
(comment "use_jtag_bufg = 1 ")
(comment "InstanceName = icon_1 ")
(comment "use_ext_trig_in = 0 ")
(comment "use_ext_trig_out = 0 ")
(comment "device_family = 0 ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell BSCAN_VIRTEX (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port RESET (direction OUTPUT))
(port UPDATE (direction OUTPUT))
(port SHIFT (direction OUTPUT))
(port DRCK1 (direction OUTPUT))
(port DRCK2 (direction OUTPUT))
(port SEL1 (direction OUTPUT))
(port SEL2 (direction OUTPUT))
(port TDI (direction OUTPUT))
(port TDO1 (direction INPUT))
(port TDO2 (direction INPUT))
)
)
)
(cell BUF (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell BUFG (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell FDC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CLR (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDCE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port CLR (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDR (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDRE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell INV (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT1 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT2 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT3 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXCY_L (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port DI (direction INPUT))
(port CI (direction INPUT))
(port S (direction INPUT))
(port LO (direction OUTPUT))
)
)
)
(cell MUXF5 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell XORCY (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port LI (direction INPUT))
(port CI (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell icon
(cellType GENERIC) (view view_1 (viewType NETLIST)
(interface
(port ( rename control0_41_ "control0<41>") (direction OUTPUT))
(port ( rename control0_40_ "control0<40>") (direction OUTPUT))
(port ( rename control0_39_ "control0<39>") (direction OUTPUT))
(port ( rename control0_38_ "control0<38>") (direction OUTPUT))
(port ( rename control0_37_ "control0<37>") (direction OUTPUT))
(port ( rename control0_36_ "control0<36>") (direction OUTPUT))
(port ( rename control0_35_ "control0<35>") (direction OUTPUT))
(port ( rename control0_34_ "control0<34>") (direction OUTPUT))
(port ( rename control0_33_ "control0<33>") (direction OUTPUT))
(port ( rename control0_32_ "control0<32>") (direction OUTPUT))
(port ( rename control0_31_ "control0<31>") (direction OUTPUT))
(port ( rename control0_30_ "control0<30>") (direction OUTPUT))
(port ( rename control0_29_ "control0<29>") (direction OUTPUT))
(port ( rename control0_28_ "control0<28>") (direction OUTPUT))
(port ( rename control0_27_ "control0<27>") (direction OUTPUT))
(port ( rename control0_26_ "control0<26>") (direction OUTPUT))
(port ( rename control0_25_ "control0<25>") (direction OUTPUT))
(port ( rename control0_24_ "control0<24>") (direction OUTPUT))
(port ( rename control0_23_ "control0<23>") (direction OUTPUT))
(port ( rename control0_22_ "control0<22>") (direction OUTPUT))
(port ( rename control0_21_ "control0<21>") (direction OUTPUT))
(port ( rename control0_20_ "control0<20>") (direction OUTPUT))
(port ( rename control0_19_ "control0<19>") (direction OUTPUT))
(port ( rename control0_18_ "control0<18>") (direction OUTPUT))
(port ( rename control0_17_ "control0<17>") (direction OUTPUT))
(port ( rename control0_16_ "control0<16>") (direction OUTPUT))
(port ( rename control0_15_ "control0<15>") (direction OUTPUT))
(port ( rename control0_14_ "control0<14>") (direction INPUT))
(port ( rename control0_13_ "control0<13>") (direction OUTPUT))
(port ( rename control0_12_ "control0<12>") (direction OUTPUT))
(port ( rename control0_11_ "control0<11>") (direction OUTPUT))
(port ( rename control0_10_ "control0<10>") (direction OUTPUT))
(port ( rename control0_9_ "control0<9>") (direction OUTPUT))
(port ( rename control0_8_ "control0<8>") (direction OUTPUT))
(port ( rename control0_7_ "control0<7>") (direction OUTPUT))
(port ( rename control0_6_ "control0<6>") (direction OUTPUT))
(port ( rename control0_5_ "control0<5>") (direction OUTPUT))
(port ( rename control0_4_ "control0<4>") (direction OUTPUT))
(port ( rename control0_3_ "control0<3>") (direction INPUT))
(port ( rename control0_2_ "control0<2>") (direction INPUT))
(port ( rename control0_1_ "control0<1>") (direction OUTPUT))
(port ( rename control0_0_ "control0<0>") (direction OUTPUT))
)
(contents
(instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
(instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
(instance (rename icon_1_u_icon_core_tap_tap "icon_1/u_icon_core/tap/tap")
(viewRef view_1 (cellRef BSCAN_VIRTEX (libraryRef xilinxun)))
)
(instance (rename icon_1_u_icon_core_bufg_if_u_drck1_buf "icon_1/u_icon_core/bufg_if/u_drck1_buf")
(viewRef view_1 (cellRef BUFG (libraryRef xilinxun)))
)
(instance (rename icon_1_u_icon_core_u_tdi_reg "icon_1/u_icon_core/u_tdi_reg")
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
)
(instance (rename icon_1_u_icon_core_u_tdo1 "icon_1/u_icon_core/u_tdo1")
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
)
(instance (rename icon_1_u_icon_core_u_sel1_n "icon_1/u_icon_core/u_sel1_n")
(viewRef view_1 (cellRef INV (libraryRef xilinxun)))
)
(instance (rename icon_1_u_icon_core_u_target_ce "icon_1/u_icon_core/u_target_ce")
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