// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 19:13:19 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module d_register (CLK, DATA, Q);    input CLK;    input DATA;    output Q;    wire n35, n36, \Q_reg/$1I11/QINT , \Q_reg/$1I11/OBUF_GTS_TRI ,     \U18/clkio_bufsig , \Q_reg/$1I11/OBUF_GTS_TRI_2_INV , GND, VCC;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U19 (.IN (DATA), .OUT (n36));    X_IPAD CLK_PAD (.PAD (CLK));    X_IPAD DATA_PAD (.PAD (DATA));    X_OPAD Q_PAD (.PAD (Q));    X_FF \Q_reg/$1I11/FF  (.IN (n36), .CLK (n35), .CE (VCC), .SET (GND), .RST     (GSR), .OUT (\Q_reg/$1I11/QINT ));    X_BUF \Q_reg/$1I11/OBUF  (.IN (\Q_reg/$1I11/QINT ), .OUT     (\Q_reg/$1I11/OBUF_GTS_TRI ));    X_TRI \Q_reg/$1I11/OBUF_GTS_TRI_13  (.IN (\Q_reg/$1I11/OBUF_GTS_TRI ), .OUT     (Q), .CTL (\Q_reg/$1I11/OBUF_GTS_TRI_2_INV ));    X_CKBUF \U18/clkbuf  (.IN (\U18/clkio_bufsig ), .OUT (n35));    X_BUF \U18/clkio_buf  (.IN (CLK), .OUT (\U18/clkio_bufsig ));    X_INV \Q_reg/$1I11/OBUF_GTS_TRI_2_INV_14  (.IN (GTS), .OUT     (\Q_reg/$1I11/OBUF_GTS_TRI_2_INV ));    X_ONE VCC_15 (.OUT (VCC));    X_ZERO GND_16 (.OUT (GND));    X_PD NGD2VER_PD_10 (.OUT (GTS) );    X_PD NGD2VER_PD_12 (.OUT (GSR) );  endmodule