////////////////////////////////////////////     // D_REGISTER.V Version 1.0               //    // Example of a behavioral description of //   // a D register.                          //  // HDL Synthesis Design Guide for FPGAs   // // May 1997                               //////////////////////////////////////////////module d_register (CLK, DATA, Q);    input  CLK;    input  DATA;    output Q;    reg    Q;    always @ (posedge CLK)    begin: My_D_Reg   	  Q <= DATA;    end endmodule