--
--
--------------------------------------------------------------------------------/
-- DESCRIPTION   :  Signed divider
--                  A (A) input width : 4
--                  B (B) input width : 4
--                  Q (data_out) output width : 4
--                  DIV_BY_0 (DIVz) output active : high
-- Download from :  http://www.pld.com.cn
--------------------------------------------------------------------------------/



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity fpdiv is
	port (
		DIVz: out STD_LOGIC;
		A: in STD_LOGIC_VECTOR (3 downto 0);
		B: in STD_LOGIC_VECTOR (3 downto 0);
		data_out: out STD_LOGIC_VECTOR (3 downto 0)
	);
end fpdiv;


architecture fpdiv_arch of fpdiv is
signal REMAINDERS0 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS1 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS2 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS3 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS0 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS1 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS2 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS3 : STD_LOGIC_VECTOR (5 downto 0);

signal Q_TEMP : STD_LOGIC_VECTOR (3 downto 0);
signal Z0 : STD_LOGIC_VECTOR (2 downto 0);
signal Z1 : STD_LOGIC_VECTOR (2 downto 0);
signal ZERO : STD_LOGIC;

begin


	Z0 <= (others => '0');
	Z1 <= (others => '0');
	DIVISORS0 <= Z0 & B(2 downto 0);
	REMAINDERS3  <= Z1 & A(2 downto 0);

	DIVISORS1 <= DIVISORS0(4 downto 0) & '0';
	DIVISORS2 <= DIVISORS1(4 downto 0) & '0';
	DIVISORS3 <= DIVISORS2(4 downto 0) & '0';

	Q_TEMP(0) <= '1' when (REMAINDERS1 >= DIVISORS0) else '0';
	Q_TEMP(1) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';
	Q_TEMP(2) <= '1' when (REMAINDERS3 >= DIVISORS2) else '0';
	Q_TEMP(3) <= A(3) xor B(3);


	REMAINDERS2 <= REMAINDERS3 - DIVISORS2 when Q_TEMP(2) = '1' else REMAINDERS3;
	REMAINDERS1 <= REMAINDERS2 - DIVISORS1 when Q_TEMP(1) = '1' else REMAINDERS2;
	REMAINDERS0 <= REMAINDERS1 - DIVISORS0 when Q_TEMP(0) = '1' else REMAINDERS1;

	ZERO <= '1' when B(2 downto 0) = Z1 else '0';
	DIVz <= '1' when ZERO = '1' else '0';
	data_out <= (others => '0') when ZERO = '1' else Q_TEMP;
end fpdiv_arch;