?? ch9_3_1.rpt
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Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 06/15/2000 18:15:16
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CH9_3_1
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
ch9_3_1 EPF10K10TC144-3 11 38 0 0 0 % 224 38 %
User Pins: 11 38 0
Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'Din7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
ch9_3_1@55 CP
ch9_3_1@131 Din0
ch9_3_1@132 Din1
ch9_3_1@133 Din2
ch9_3_1@135 Din3
ch9_3_1@136 Din4
ch9_3_1@137 Din5
ch9_3_1@138 Din6
ch9_3_1@140 Din7
ch9_3_1@38 nCS
ch9_3_1@143 nINTR
ch9_3_1@128 nRD
ch9_3_1@124 RST
ch9_3_1@23 SEGOUT0
ch9_3_1@26 SEGOUT1
ch9_3_1@27 SEGOUT2
ch9_3_1@28 SEGOUT3
ch9_3_1@29 SEGOUT4
ch9_3_1@30 SEGOUT5
ch9_3_1@31 SEGOUT6
ch9_3_1@32 SEGOUT7
ch9_3_1@33 SELOUT0
ch9_3_1@36 SELOUT1
ch9_3_1@37 SELOUT2
Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
** STATE MACHINE ASSIGNMENTS **
State: MACHINE
OF BITS (
State~4,
State~3,
State~2,
State~1
)
WITH STATES (
S0 = B"0000",
S1 = B"1100",
S2 = B"1010",
S3 = B"1001"
);
Project Information d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
** FILE HIERARCHY **
|lpm_add_sub:470|
|lpm_add_sub:470|addcore:adder|
|lpm_add_sub:470|altshift:result_ext_latency_ffs|
|lpm_add_sub:470|altshift:carry_ext_latency_ffs|
|lpm_add_sub:470|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:694|
|lpm_add_sub:694|addcore:adder|
|lpm_add_sub:694|altshift:result_ext_latency_ffs|
|lpm_add_sub:694|altshift:carry_ext_latency_ffs|
|lpm_add_sub:694|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
***** Logic for device 'ch9_3_1' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R
E E E E E E E E E E E E E
S S S G G G V S S S S S S S S S S
E n E T G V E G N N N C E E E T E E E V E E T T E E
R I R o D N D D D D C D D D R N D D D C R R R o R R R C R R o o R R
V N V u i D i i i i C i i i V D n I I I R I V V V u V V V C V V u u V V
E T E t n I n n n n I n n n E I R N N N S N E E E t E E E I E E t t E E
D R D 7 7 O 6 5 4 3 O 2 1 0 D O D T T T T T D D D 4 D D D O D D 2 6 D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
Tout9 | 7 102 | Tout11
Temp7 | 8 101 | Temp1
Tout10 | 9 100 | Temp0
Temp5 | 10 99 | RESERVED
Temp4 | 11 98 | RESERVED
nWR | 12 97 | Temp6
Temp2 | 13 96 | RESERVED
Temp3 | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K10TC144-3 90 | RESERVED
Tout8 | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
SEGOUT0 | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
SEGOUT1 | 26 83 | Dout0
SEGOUT2 | 27 82 | Tout5
SEGOUT3 | 28 81 | Dout1
SEGOUT4 | 29 80 | Dout2
SEGOUT5 | 30 79 | Tout1
SEGOUT6 | 31 78 | Tout3
SEGOUT7 | 32 77 | ^MSEL0
SELOUT0 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
SELOUT1 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
S n D G T R R R V R R R R G R V V G C G G G R R V R R R R G R R R R V R
E C o N o E E E C E E E E N E C C N P N N N E E C E E E E N E E E E C E
L S u D u S S S C S S S S D S C C D D D D S S C S S S S D S S S S C S
O t I t E E E I E E E E I E I I I I I I E E I E E E E I E E E E I E
U 3 O 0 R R R O R R R R O R N N N N N N R R O R R R R O R R R R O R
T V V V V V V V V T T T T T T V V V V V V V V V V V
2 E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 3/ 8( 37%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
A2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A3 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A4 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
A5 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A6 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
A7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A9 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
A10 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
A11 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
A12 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A13 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
A14 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A15 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
A16 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
A17 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A18 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
A19 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
A20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A21 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
A22 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
A23 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
A24 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B4 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B6 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
B7 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B11 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
B12 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B13 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B14 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
B15 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
B16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
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