?? ch9_3_1.rpt
字號:
B17 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B18 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B20 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
B21 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
B22 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B23 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
B24 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
C2 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C3 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C6 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
C8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
C9 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C10 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C11 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C13 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
C15 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C20 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C21 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C22 3/ 8( 37%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C23 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 47/96 ( 48%)
Total logic cells used: 224/576 ( 38%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.33/4 ( 83%)
Total fan-in: 747/2304 ( 32%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 38
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 224
Total flipflops required: 31
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 59/ 576 ( 10%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 3 1 2 8 2 2 2 8 2 6 3 6 0 3 8 2 2 2 2 2 1 3 2 2 3 77/0
B: 0 0 0 6 1 5 6 1 1 1 5 7 0 4 2 4 8 3 4 2 3 2 2 6 3 76/0
C: 0 6 7 1 0 3 0 8 1 1 5 1 0 6 0 8 1 1 1 1 8 1 3 7 1 71/0
Total: 3 7 9 15 3 10 8 17 4 8 13 14 0 13 10 14 11 6 7 5 12 6 7 15 7 224/0
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 CP
131 - - - 15 INPUT 0 0 0 1 Din0
132 - - - 16 INPUT 0 0 0 1 Din1
133 - - - 17 INPUT 0 0 0 1 Din2
135 - - - 18 INPUT 0 0 0 1 Din3
136 - - - 19 INPUT 0 0 0 1 Din4
137 - - - 19 INPUT 0 0 0 1 Din5
138 - - - 20 INPUT 0 0 0 1 Din6
140 - - - 21 INPUT 0 0 0 0 Din7
143 - - - 24 INPUT 0 0 0 2 nINTR
124 - - - -- INPUT G 0 0 0 0 RST
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - C -- OUTPUT 0 1 0 0 Dout0
81 - - C -- OUTPUT 0 1 0 0 Dout1
80 - - C -- OUTPUT 0 1 0 0 Dout2
39 - - - 21 OUTPUT 0 1 0 0 Dout3
38 - - - 22 OUTPUT 0 1 0 0 nCS
128 - - - 13 OUTPUT 0 1 0 0 nRD
12 - - A -- OUTPUT 0 1 0 0 nWR
23 - - B -- OUTPUT 0 1 0 0 SEGOUT0
26 - - C -- OUTPUT 0 1 0 0 SEGOUT1
27 - - C -- OUTPUT 0 1 0 0 SEGOUT2
28 - - C -- OUTPUT 0 1 0 0 SEGOUT3
29 - - C -- OUTPUT 0 1 0 0 SEGOUT4
30 - - C -- OUTPUT 0 1 0 0 SEGOUT5
31 - - C -- OUTPUT 0 1 0 0 SEGOUT6
32 - - C -- OUTPUT 0 0 0 0 SEGOUT7
33 - - C -- OUTPUT 0 1 0 0 SELOUT0
36 - - - 24 OUTPUT 0 1 0 0 SELOUT1
37 - - - 23 OUTPUT 0 1 0 0 SELOUT2
100 - - A -- OUTPUT 0 0 0 0 Temp0
101 - - A -- OUTPUT 0 1 0 0 Temp1
13 - - A -- OUTPUT 0 1 0 0 Temp2
14 - - A -- OUTPUT 0 1 0 0 Temp3
11 - - A -- OUTPUT 0 1 0 0 Temp4
10 - - A -- OUTPUT 0 1 0 0 Temp5
97 - - A -- OUTPUT 0 1 0 0 Temp6
8 - - A -- OUTPUT 0 1 0 0 Temp7
41 - - - 20 OUTPUT 0 1 0 0 Tout0
79 - - C -- OUTPUT 0 1 0 0 Tout1
112 - - - 03 OUTPUT 0 1 0 0 Tout2
78 - - C -- OUTPUT 0 1 0 0 Tout3
119 - - - 08 OUTPUT 0 1 0 0 Tout4
82 - - C -- OUTPUT 0 1 0 0 Tout5
111 - - - 02 OUTPUT 0 1 0 0 Tout6
141 - - - 22 OUTPUT 0 1 0 0 Tout7
20 - - B -- OUTPUT 0 1 0 0 Tout8
7 - - A -- OUTPUT 0 0 0 0 Tout9
9 - - A -- OUTPUT 0 0 0 0 Tout10
102 - - A -- OUTPUT 0 0 0 0 Tout11
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 20 AND2 0 3 0 4 |LPM_ADD_SUB:470|addcore:adder|:107
- 1 - C 20 AND2 0 4 0 4 |LPM_ADD_SUB:470|addcore:adder|:119
- 2 - C 15 AND2 0 4 0 4 |LPM_ADD_SUB:470|addcore:adder|:131
- 1 - C 15 AND2 0 4 0 4 |LPM_ADD_SUB:470|addcore:adder|:143
- 4 - C 23 AND2 0 2 0 1 |LPM_ADD_SUB:470|addcore:adder|:147
- 3 - A 24 AND2 ! 0 3 0 3 |LPM_ADD_SUB:694|addcore:adder|pcarry3
- 4 - A 14 OR2 0 4 0 3 |LPM_ADD_SUB:694|addcore:adder|:87
- 7 - A 17 OR2 0 2 1 0 |LPM_ADD_SUB:694|addcore:adder|:108
- 8 - A 13 OR2 0 3 1 0 |LPM_ADD_SUB:694|addcore:adder|:109
- 5 - A 13 OR2 0 4 1 0 |LPM_ADD_SUB:694|addcore:adder|:110
- 3 - A 14 OR2 0 2 1 0 |LPM_ADD_SUB:694|addcore:adder|:111
- 6 - A 14 OR2 0 3 1 0 |LPM_ADD_SUB:694|addcore:adder|:112
- 2 - A 14 OR2 0 4 1 0 |LPM_ADD_SUB:694|addcore:adder|:113
- 3 - A 21 DFFE + 0 1 0 1 State~1
- 2 - A 23 DFFE + 1 1 0 4 State~2
- 4 - A 22 DFFE + 1 1 0 4 State~3
- 2 - A 21 DFFE + 0 1 0 5 State~4
- 1 - A 21 DFFE + ! 0 3 1 0 :46
- 6 - A 19 DFFE + ! 0 1 1 0 :48
- 1 - A 13 DFFE + ! 0 3 1 0 :50
- 2 - A 18 DFFE + 0 3 0 7 EC (:93)
- 7 - A 14 DFFE + 1 1 0 3 D6 (:95)
- 2 - A 16 DFFE + 1 1 0 37 D5 (:96)
- 8 - A 14 DFFE + 1 1 0 5 D4 (:97)
- 1 - A 17 DFFE + 1 1 0 22 D3 (:98)
- 2 - A 22 DFFE + 1 1 0 12 D2 (:99)
- 5 - A 16 DFFE + 1 1 0 20 D1 (:100)
- 2 - A 15 DFFE + 1 1 1 37 D0 (:101)
- 3 - C 23 DFFE + 0 3 0 6 Q15 (:119)
- 7 - C 23 DFFE + 0 3 0 8 Q14 (:120)
- 6 - C 23 DFFE + 0 2 0 2 Q13 (:121)
- 5 - C 23 DFFE + 0 1 0 3 Q12 (:122)
- 8 - C 15 DFFE + 0 3 0 1 Q11 (:123)
- 7 - C 15 DFFE + 0 2 0 2 Q10 (:124)
- 6 - C 15 DFFE + 0 1 0 3 Q9 (:125)
- 5 - C 15 DFFE + 0 3 0 1 Q8 (:126)
- 4 - C 15 DFFE + 0 2 0 2 Q7 (:127)
- 3 - C 15 DFFE + 0 1 0 3 Q6 (:128)
- 8 - C 20 DFFE + 0 3 0 1 Q5 (:129)
- 7 - C 20 DFFE + 0 2 0 2 Q4 (:130)
- 6 - C 20 DFFE + 0 1 0 3 Q3 (:131)
- 5 - C 20 DFFE + 0 2 0 1 Q2 (:132)
- 4 - C 20 DFFE + 0 1 0 2 Q1 (:133)
- 3 - C 20 DFFE + 0 0 0 3 Q0 (:134)
- 6 - C 03 OR2 ! 0 4 0 3 :728
- 2 - C 03 OR2 ! 0 4 0 3 :746
- 7 - C 03 OR2 ! 0 3 0 1 :764
- 3 - C 12 OR2 ! 0 3 0 2 :782
- 7 - A 05 AND2 s 0 3 0 4 ~800~1
- 3 - C 04 OR2 ! 0 3 0 5 :800
- 1 - C 11 AND2 0 4 0 2 :818
- 6 - A 01 AND2 s ! 0 3 0 10 ~836~1
- 2 - C 11 AND2 0 3 0 1 :836
- 1 - A 01 AND2 s ! 0 4 0 5 ~854~1
- 3 - A 01 AND2 0 4 0 2 :872
- 4 - A 19 AND2 0 4 0 5 :890
- 1 - A 12 OR2 ! 0 3 0 1 :908
- 3 - A 07 OR2 ! 0 4 0 2 :926
- 2 - A 12 OR2 ! 0 4 0 2 :944
- 5 - A 12 OR2 ! 0 4 0 2 :962
- 1 - A 05 OR2 ! 0 4 0 5 :980
- 1 - A 07 AND2 0 4 0 4 :1016
- 5 - A 08 OR2 ! 0 3 0 1 :1034
- 6 - A 08 AND2 0 3 0 2 :1052
- 1 - A 24 OR2 s ! 0 2 0 18 ~1070~1
- 1 - A 09 AND2 0 2 0 6 :1070
- 2 - A 03 OR2 ! 0 3 0 2 :1088
- 3 - A 08 AND2 0 3 0 1 :1106
- 4 - A 08 OR2 ! 0 3 0 1 :1124
- 2 - A 24 OR2 ! 0 4 0 2 :1142
- 3 - C 09 OR2 ! 0 4 0 5 :1160
- 1 - A 14 AND2 s ! 0 2 0 14 ~1178~1
- 5 - B 12 AND2 0 4 0 2 :1178
- 1 - C 10 AND2 s ! 0 2 0 19 ~1196~1
- 3 - B 12 AND2 0 3 0 1 :1196
- 2 - B 08 OR2 s 0 4 0 4 ~1214~1
- 2 - B 12 AND2 0 4 0 2 :1232
- 1 - B 09 AND2 0 3 0 5 :1250
- 1 - A 23 OR2 s 0 2 0 8 ~1268~1
- 8 - B 17 AND2 s ! 0 3 0 7 ~1268~2
- 2 - B 04 OR2 ! 0 2 0 1 :1268
- 1 - B 04 AND2 0 2 0 1 :1286
- 1 - A 15 AND2 s ! 0 3 0 9 ~1322~1
- 3 - B 04 OR2 ! 0 4 0 2 :1322
- 2 - A 06 OR2 ! 0 3 0 5 :1340
- 1 - A 06 AND2 s ! 0 4 0 3 ~1358~1
- 1 - A 04 AND2 0 3 0 2 :1358
- 8 - A 04 AND2 0 3 0 1 :1376
- 4 - A 04 AND2 0 4 0 2 :1394
- 7 - A 04 AND2 0 3 0 1 :1412
- 5 - A 14 OR2 s ! 0 2 0 12 ~1430~1
- 6 - B 20 AND2 0 4 0 5 :1430
- 2 - A 20 OR2 s 0 2 0 6 ~1448~1
- 3 - B 18 OR2 ! 0 4 0 2 :1448
- 1 - A 18 OR2 s 0 3 0 8 ~1466~1
- 4 - B 18 OR2 ! 0 4 0 2 :1466
- 7 - B 16 OR2 ! 0 3 0 2 :1484
- 8 - B 16 AND2 0 2 0 1 :1502
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