?? ch9_3_1.rpt
字號(hào):
- 1 - B 21 OR2 s ! 0 2 0 6 ~1520~1
- 4 - B 14 OR2 ! 0 4 0 6 :1520
- 5 - B 20 AND2 s 0 3 0 4 ~1574~1
- 1 - B 19 AND2 s 0 3 0 4 ~1592~1
- 4 - B 13 AND2 0 4 0 2 :1610
- 1 - B 18 AND2 s ! 0 2 0 2 ~3191~1
- 4 - A 03 OR2 s ! 0 4 0 2 ~3433~1
- 2 - C 02 OR2 s ! 0 4 0 3 ~3433~2
- 5 - B 21 OR2 0 4 1 1 :3433
- 5 - A 10 OR2 s ! 0 4 0 2 ~3614~1
- 2 - B 07 OR2 s 0 4 0 2 ~3614~2
- 6 - B 07 OR2 s 0 2 0 1 ~3614~3
- 4 - C 02 OR2 0 2 0 2 :3614
- 3 - C 02 AND2 0 4 1 1 :3736
- 4 - B 04 OR2 s ! 0 3 0 2 ~3857~1
- 2 - B 24 OR2 s 0 2 0 1 ~3857~2
- 1 - B 05 OR2 0 4 0 2 :3857
- 6 - A 10 OR2 s 0 4 0 2 ~3925~1
- 5 - C 02 OR2 s 0 4 0 1 ~3977~1
- 6 - C 02 OR2 s ! 0 4 0 3 ~4039~1
- 8 - C 08 OR2 s ! 0 2 0 1 ~4039~2
- 1 - C 02 OR2 0 4 1 1 :4039
- 3 - B 13 OR2 s 0 4 0 1 ~4070~1
- 1 - B 13 OR2 0 4 0 4 :4070
- 3 - B 16 OR2 s 0 3 0 2 ~4108~1
- 3 - A 04 OR2 s 0 4 0 2 ~4130~1
- 1 - B 24 OR2 0 4 0 1 :4130
- 4 - B 12 OR2 s 0 3 0 2 ~4190~1
- 1 - B 07 OR2 0 4 0 1 :4190
- 3 - C 08 AND2 s 0 2 0 1 ~4228~1
- 2 - A 08 OR2 s 0 4 0 3 ~4250~1
- 4 - C 08 OR2 0 4 0 1 :4250
- 4 - A 12 AND2 s 0 2 0 2 ~4288~1
- 5 - C 08 AND2 0 3 0 1 :4288
- 1 - C 06 OR2 s 0 3 0 2 ~4310~1
- 1 - C 08 OR2 0 4 1 1 :4342
- 2 - B 13 OR2 0 4 0 1 :4409
- 1 - B 16 AND2 s 0 2 0 5 ~4411~1
- 5 - B 10 OR2 s ! 0 2 0 3 ~4441~1
- 1 - B 11 OR2 s 0 4 0 2 ~4471~1
- 5 - B 11 AND2 s 0 2 0 3 ~4471~2
- 4 - B 07 OR2 0 4 0 1 :4471
- 3 - B 07 OR2 0 4 0 1 :4499
- 5 - B 07 OR2 s ! 0 2 0 3 ~4501~1
- 1 - A 10 AND2 s 0 2 0 3 ~4531~1
- 2 - A 09 OR2 s ! 0 4 0 3 ~4561~1
- 6 - C 08 OR2 0 4 0 1 :4561
- 2 - C 08 OR2 0 4 0 1 :4589
- 2 - A 11 AND2 s 0 2 0 5 ~4591~1
- 4 - C 06 OR2 s ! 0 2 0 3 ~4621~1
- 4 - C 03 AND2 s 0 3 0 3 ~4645~1
- 7 - C 08 OR2 0 4 1 1 :4645
- 6 - B 16 OR2 0 4 0 1 :4664
- 5 - B 17 OR2 s 0 4 0 2 ~4690~1
- 5 - B 16 OR2 0 4 0 1 :4690
- 4 - B 16 OR2 0 4 0 1 :4720
- 6 - A 04 OR2 s ! 0 4 0 2 ~4750~1
- 4 - B 11 OR2 0 4 0 1 :4750
- 2 - B 11 OR2 0 4 0 1 :4780
- 6 - B 12 OR2 s ! 0 4 0 2 ~4810~1
- 3 - B 11 OR2 0 4 0 1 :4810
- 4 - A 10 OR2 0 4 0 1 :4840
- 3 - A 10 OR2 s 0 3 0 1 ~4870~1
- 2 - A 10 OR2 0 4 0 1 :4870
- 1 - A 11 OR2 s 0 4 0 2 ~4900~1
- 7 - A 11 OR2 0 4 0 1 :4900
- 8 - C 11 OR2 s ! 0 4 0 2 ~4930~1
- 5 - C 06 OR2 0 4 0 1 :4930
- 3 - C 03 OR2 0 4 1 1 :4948
- 1 - B 14 OR2 0 3 0 2 :4973
- 2 - B 16 OR2 0 4 0 1 :5005
- 2 - B 18 OR2 0 4 0 1 :5023
- 2 - A 04 OR2 0 3 0 1 :5035
- 5 - A 04 OR2 0 4 0 1 :5053
- 6 - B 04 OR2 0 4 0 1 :5065
- 5 - B 04 OR2 0 4 0 1 :5083
- 7 - B 12 OR2 0 4 0 1 :5095
- 1 - B 12 OR2 0 4 0 1 :5113
- 7 - A 08 OR2 0 4 0 1 :5123
- 8 - A 08 OR2 0 4 0 1 :5141
- 1 - A 08 OR2 0 4 0 1 :5173
- 6 - A 12 OR2 0 4 0 1 :5183
- 3 - A 12 OR2 0 4 0 1 :5201
- 4 - C 11 OR2 0 4 0 1 :5213
- 3 - C 11 OR2 0 4 0 1 :5231
- 5 - C 03 OR2 0 4 1 1 :5251
- 1 - C 03 OR2 s ! 0 4 0 2 ~5552~1
- 7 - A 02 OR2 s 0 3 0 2 ~5552~2
- 3 - B 24 OR2 s 0 4 1 0 ~5552~3
- 7 - B 20 OR2 0 4 1 1 :5552
- 2 - C 23 AND2 0 2 1 0 :5602
- 1 - C 23 OR2 0 2 1 0 :5612
- 7 - C 24 AND2 0 1 1 0 :5626
- 3 - C 21 OR2 0 4 1 19 :5731
- 4 - C 22 OR2 0 4 1 19 :5740
- 3 - C 22 OR2 0 4 1 21 :5749
- 1 - C 22 OR2 0 4 1 20 :5758
- 2 - C 13 AND2 0 4 0 2 :5777
- 3 - C 13 OR2 ! 0 4 0 2 :5782
- 6 - C 13 AND2 0 4 0 1 :5787
- 5 - B 23 OR2 ! 0 4 0 1 :5792
- 2 - B 22 OR2 ! 0 4 0 2 :5797
- 4 - B 23 OR2 ! 0 4 0 1 :5802
- 3 - B 23 AND2 0 4 0 1 :5807
- 1 - B 22 OR2 ! 0 4 0 2 :5812
- 1 - B 17 AND2 s 0 2 0 4 ~5817~1
- 2 - B 23 AND2 0 3 0 1 :5817
- 4 - B 06 OR2 ! 0 3 0 1 :5822
- 3 - B 06 AND2 0 3 0 1 :5827
- 1 - B 06 AND2 0 4 0 1 :5852
- 6 - C 19 OR2 0 4 1 0 :5958
- 3 - B 15 OR2 0 2 0 1 :5983
- 4 - B 15 OR2 0 4 0 1 :5995
- 5 - C 13 OR2 0 4 1 0 :6007
- 2 - B 06 OR2 0 4 0 1 :6036
- 6 - B 23 OR2 0 4 0 1 :6040
- 1 - B 23 AND2 0 4 0 1 :6054
- 4 - C 13 OR2 0 4 1 0 :6058
- 5 - B 06 OR2 0 4 0 1 :6076
- 3 - C 17 OR2 0 4 1 0 :6109
- 1 - C 16 OR2 0 4 1 0 :6160
- 1 - C 18 OR2 0 4 1 0 :6211
- 1 - B 15 OR2 0 4 0 1 :6226
- 2 - B 15 OR2 s 0 4 0 1 ~6247~1
- 1 - C 13 OR2 s ! 0 3 0 1 ~6256~1
- 7 - B 19 OR2 0 4 1 0 :6262
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 19/ 48( 39%) 19/ 48( 39%) 0/16( 0%) 12/16( 75%) 0/16( 0%)
B: 23/ 96( 23%) 13/ 48( 27%) 16/ 48( 33%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 16/ 96( 16%) 26/ 48( 54%) 19/ 48( 39%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
22: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RST
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_3_1.rpt
ch9_3_1
** EQUATIONS **
CP : INPUT;
Din0 : INPUT;
Din1 : INPUT;
Din2 : INPUT;
Din3 : INPUT;
Din4 : INPUT;
Din5 : INPUT;
Din6 : INPUT;
Din7 : INPUT;
nINTR : INPUT;
RST : INPUT;
-- Node name is 'Dout0'
-- Equation name is 'Dout0', type is output
Dout0 = _LC1_C22;
-- Node name is 'Dout1'
-- Equation name is 'Dout1', type is output
Dout1 = _LC3_C22;
-- Node name is 'Dout2'
-- Equation name is 'Dout2', type is output
Dout2 = _LC4_C22;
-- Node name is 'Dout3'
-- Equation name is 'Dout3', type is output
Dout3 = _LC3_C21;
-- Node name is ':101' = 'D0'
-- Equation name is 'D0', location is LC2_A15, type is buried.
D0 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = D0 & !EC
# Din0 & EC;
-- Node name is ':100' = 'D1'
-- Equation name is 'D1', location is LC5_A16, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = D1 & !EC
# Din1 & EC;
-- Node name is ':99' = 'D2'
-- Equation name is 'D2', location is LC2_A22, type is buried.
D2 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = D2 & !EC
# Din2 & EC;
-- Node name is ':98' = 'D3'
-- Equation name is 'D3', location is LC1_A17, type is buried.
D3 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = D3 & !EC
# Din3 & EC;
-- Node name is ':97' = 'D4'
-- Equation name is 'D4', location is LC8_A14, type is buried.
D4 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = D4 & !EC
# Din4 & EC;
-- Node name is ':96' = 'D5'
-- Equation name is 'D5', location is LC2_A16, type is buried.
D5 = DFFE( _EQ006, GLOBAL( CP), VCC, VCC, VCC);
_EQ006 = D5 & !EC
# Din5 & EC;
-- Node name is ':95' = 'D6'
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