?? ch9_2_3.rpt
字號:
- 6 - A 14 DFFE + 0 2 0 2 Q13 (:157)
- 5 - A 14 DFFE + 0 1 0 3 Q12 (:158)
- 3 - A 14 DFFE + 0 3 0 1 Q11 (:159)
- 1 - A 14 DFFE + 0 2 0 2 Q10 (:160)
- 1 - A 24 DFFE + 0 1 0 3 Q9 (:161)
- 2 - A 21 DFFE + 0 3 0 1 Q8 (:162)
- 3 - A 21 DFFE + 0 2 0 2 Q7 (:163)
- 5 - A 21 DFFE + 0 1 0 3 Q6 (:164)
- 1 - A 20 DFFE + 0 3 0 1 Q5 (:165)
- 3 - A 20 DFFE + 0 2 0 2 Q4 (:166)
- 4 - A 20 DFFE + 0 1 0 3 Q3 (:167)
- 5 - A 20 DFFE + 0 2 0 1 Q2 (:168)
- 6 - A 20 DFFE + 0 1 0 2 Q1 (:169)
- 8 - A 20 DFFE + 0 0 0 3 Q0 (:170)
- 5 - B 07 OR2 ! 0 4 0 3 :769
- 6 - B 07 AND2 0 4 0 3 :778
- 6 - B 05 OR2 ! 0 4 0 3 :787
- 4 - B 05 OR2 ! 0 4 0 5 :796
- 3 - A 05 AND2 0 3 0 6 :805
- 2 - A 06 AND2 0 3 0 3 :814
- 1 - A 01 AND2 s ! 0 2 0 6 ~823~1
- 3 - A 04 OR2 ! 0 3 0 2 :823
- 5 - A 08 AND2 0 3 0 3 :832
- 1 - A 03 OR2 ! 0 4 0 3 :841
- 4 - A 10 OR2 ! 0 4 0 1 :850
- 7 - B 05 OR2 s ! 0 3 0 3 ~1041~1
- 5 - B 05 AND2 ! 0 2 0 4 :1041
- 7 - A 02 OR2 s ! 0 4 0 2 ~1080~1
- 6 - A 07 AND2 s ! 0 2 0 1 ~1080~2
- 8 - A 02 OR2 0 4 0 2 :1080
- 6 - A 02 OR2 0 4 0 1 :1110
- 1 - A 02 OR2 s 0 3 0 1 ~1128~1
- 2 - A 02 OR2 0 4 0 3 :1128
- 7 - B 07 OR2 s 0 4 0 1 ~1187~1
- 2 - A 10 OR2 0 4 0 1 :1203
- 3 - A 10 OR2 0 4 0 1 :1212
- 3 - A 11 OR2 s 0 3 0 3 ~1223~1
- 2 - B 05 AND2 s 0 2 0 3 ~1232~1
- 1 - A 10 OR2 0 4 0 2 :1232
- 1 - A 07 OR2 0 4 0 1 :1259
- 2 - A 07 OR2 0 4 0 1 :1268
- 3 - A 07 OR2 0 4 0 2 :1283
- 1 - B 10 OR2 0 4 0 1 :1379
- 4 - A 07 OR2 s 0 4 0 1 ~1418~1
- 5 - A 07 AND2 0 3 0 2 :1418
- 3 - B 05 OR2 0 3 0 2 :1427
- 1 - A 11 OR2 0 4 0 1 :1454
- 2 - A 11 OR2 0 4 0 1 :1461
- 1 - B 05 OR2 0 4 0 4 :1475
- 5 - B 22 AND2 0 4 0 3 :1528
- 6 - B 22 OR2 ! 0 4 0 2 :1537
- 2 - B 23 AND2 0 4 0 2 :1546
- 7 - B 22 OR2 0 4 0 1 :2070
- 8 - B 22 AND2 s 0 2 0 2 ~2090~1
- 3 - B 22 OR2 0 4 0 1 :2118
- 2 - B 21 OR2 s ! 0 3 0 5 ~2135~1
- 1 - B 22 OR2 0 4 0 1 :2138
- 5 - B 13 OR2 0 4 0 3 :2178
- 2 - B 19 AND2 s ! 0 3 0 6 ~2186~1
- 4 - B 13 OR2 s 0 4 0 2 ~2234~1
- 1 - B 04 OR2 ! 0 3 0 6 :2307
- 2 - B 04 OR2 0 3 0 8 :2358
- 2 - B 01 AND2 0 3 0 1 :2559
- 3 - B 01 OR2 0 3 0 1 :2565
- 1 - B 12 OR2 ! 0 2 0 4 :2604
- 7 - B 02 AND2 0 2 0 3 :2606
- 5 - B 09 OR2 ! 0 2 0 2 :2608
- 4 - B 09 OR2 0 4 0 1 :2717
- 5 - B 06 OR2 0 4 0 1 :2730
- 4 - B 06 OR2 0 4 0 1 :2731
- 2 - B 09 OR2 0 4 0 1 :2735
- 3 - B 06 OR2 0 4 0 1 :2738
- 1 - B 06 OR2 0 4 0 5 :2741
- 1 - B 08 OR2 0 4 0 5 :2753
- 1 - B 09 OR2 0 4 0 5 :2765
- 3 - A 02 OR2 0 4 0 1 :2923
- 4 - A 02 OR2 0 4 0 1 :2935
- 5 - A 02 OR2 ! 0 3 0 1 :2947
- 6 - C 16 OR2 ! 0 2 1 0 :2998
- 1 - C 23 AND2 0 2 1 0 :3024
- 2 - C 23 OR2 0 2 1 0 :3034
- 8 - C 23 AND2 0 1 1 0 :3048
- 3 - C 10 AND2 0 2 0 1 :3108
- 2 - B 06 OR2 0 4 0 9 :3148
- 1 - B 01 OR2 0 4 1 8 :3153
- 4 - C 03 OR2 0 4 0 5 :3159
- 2 - C 03 OR2 0 4 1 8 :3162
- 1 - C 10 OR2 0 4 0 5 :3168
- 2 - C 10 OR2 0 4 1 8 :3171
- 1 - C 12 OR2 0 4 1 12 :3182
- 5 - C 17 AND2 0 4 0 6 :3199
- 5 - C 03 OR2 ! 0 4 0 5 :3204
- 2 - C 19 AND2 0 4 0 4 :3209
- 3 - C 03 AND2 0 4 0 3 :3214
- 1 - C 07 OR2 ! 0 4 0 6 :3219
- 7 - C 03 AND2 0 4 0 2 :3224
- 5 - C 05 AND2 0 4 0 2 :3229
- 1 - C 03 AND2 0 4 0 5 :3234
- 3 - C 11 AND2 0 4 0 4 :3239
- 2 - C 06 AND2 0 4 0 4 :3244
- 2 - C 02 AND2 0 4 0 4 :3249
- 2 - C 09 OR2 ! 0 4 0 4 :3254
- 1 - C 21 AND2 0 4 0 4 :3259
- 5 - C 01 OR2 ! 0 4 0 5 :3264
- 5 - C 24 AND2 0 4 0 3 :3269
- 2 - C 04 AND2 0 4 0 3 :3274
- 4 - C 24 OR2 0 3 0 1 :3300
- 3 - C 24 OR2 0 4 0 1 :3344
- 3 - C 22 OR2 s 0 3 0 2 ~3366~1
- 4 - C 22 OR2 s ! 0 2 0 2 ~3380~1
- 5 - C 22 OR2 0 4 1 0 :3380
- 1 - C 24 OR2 0 3 0 2 :3395
- 1 - C 06 OR2 s 0 4 0 2 ~3405~1
- 2 - C 20 OR2 0 4 0 1 :3413
- 5 - C 20 OR2 0 4 1 0 :3429
- 3 - C 20 OR2 s ! 0 2 0 2 ~3431~1
- 4 - C 05 OR2 0 4 0 1 :3458
- 3 - C 05 OR2 0 4 0 1 :3462
- 2 - C 05 AND2 0 4 0 1 :3476
- 3 - C 14 OR2 0 4 1 0 :3480
- 2 - C 24 OR2 0 4 0 2 :3498
- 1 - C 04 OR2 0 4 0 1 :3507
- 3 - C 04 OR2 0 4 0 1 :3524
- 3 - C 15 OR2 0 4 1 0 :3531
- 7 - C 22 OR2 s 0 3 0 1 ~3573~1
- 6 - C 20 OR2 s 0 2 0 1 ~3573~2
- 1 - C 22 OR2 0 4 1 0 :3582
- 1 - C 08 OR2 s 0 4 0 3 ~3612~1
- 4 - C 20 OR2 0 3 0 1 :3623
- 1 - C 20 OR2 0 4 1 0 :3633
- 6 - C 22 OR2 0 3 0 1 :3656
- 1 - C 05 OR2 s 0 2 0 5 ~3669~1
- 2 - C 22 OR2 0 4 0 1 :3677
- 1 - C 18 OR2 s 0 2 0 3 ~3678~1
- 6 - B 20 OR2 0 4 1 0 :3684
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 15/ 48( 31%) 8/ 48( 16%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 17/ 96( 17%) 17/ 48( 35%) 14/ 48( 29%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 20/ 96( 20%) 14/ 48( 29%) 14/ 48( 29%) 0/16( 0%) 11/16( 68%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RST
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** EQUATIONS **
CP : INPUT;
Din0 : INPUT;
Din1 : INPUT;
Din2 : INPUT;
Din3 : INPUT;
Din4 : INPUT;
Din5 : INPUT;
Din6 : INPUT;
Din7 : INPUT;
nINTR : INPUT;
RST : INPUT;
-- Node name is 'Dout0'
-- Equation name is 'Dout0', type is output
Dout0 = _LC1_C12;
-- Node name is 'Dout1'
-- Equation name is 'Dout1', type is output
Dout1 = _LC2_C10;
-- Node name is 'Dout2'
-- Equation name is 'Dout2', type is output
Dout2 = _LC2_C3;
-- Node name is 'Dout3'
-- Equation name is 'Dout3', type is output
Dout3 = _LC1_B1;
-- Node name is ':71' = 'D0'
-- Equation name is 'D0', location is LC8_B24, type is buried.
D0 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = D0 & !EC
# Din0 & EC;
-- Node name is ':70' = 'D1'
-- Equation name is 'D1', location is LC5_B24, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = D1 & !EC
# Din1 & EC;
-- Node name is ':69' = 'D2'
-- Equation name is 'D2', location is LC4_B24, type is buried.
D2 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = D2 & !EC
# Din2 & EC;
-- Node name is ':68' = 'D3'
-- Equation name is 'D3', location is LC4_B18, type is buried.
D3 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = D3 & !EC
# Din3 & EC;
-- Node name is ':67' = 'D4'
-- Equation name is 'D4', location is LC1_A9, type is buried.
D4 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = D4 & !EC
# Din4 & EC;
-- Node name is ':66' = 'D5'
-- Equation name is 'D5', location is LC1_A12, type is buried.
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -