-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
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--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
--
--                     web: http://www.latticesemi.com/
--                     email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
--
--  Project:           Universal Asynchronous Receiver Transmitter
--  File:              uart_tx_tb.vhd
--  Title:             uart_tx_tb
--  Design Library:    IEEE, generics
--  Dependencies:      IEEE.std_logic_1164.all
--                     IEEE.numeric_std.all
--                     generics.components.all
--  Description:       VHDL test bench for UART_top transmitter testing
--                     There are 4 tests in different combinations:
--                     Test 1 : 5-bit data, even parity, 1 stop
--                     Test 2 : 5-bit data, even parity, 1.5 stop
--                     Test 3 : 5-bit data, odd parity, 1 stop
--                     Test 4 : 5-bit data, odd parity, 1.5 stop
--                     Test 5 : 5-bit data, stick even parity, 1 stop
--                     Test 6 : 5-bit data, stick even parity, 1.5 stop
--                     Test 7 : 5-bit data, stick odd parity, 1 stop
--                     Test 8 : 5-bit data, stick odd parity, 1.5 stop
--                     Test 9 : 5-bit data, no parity, 1 stop
--                     Test 10 : 5-bit data, no parity, 1.5 stop
--                     Test 11 : 6-bit data, even parity, 1 stop
--                     Test 12 : 6-bit data, even parity, 2 stop
--                     Test 13 : 6-bit data, odd parity, 1 stop
--                     Test 14 : 6-bit data, odd parity, 2 stop
--                     Test 15 : 6-bit data, stick even parity, 1 stop
--                     Test 16 : 6-bit data, stick even parity, 2 stop
--                     Test 17 : 6-bit data, stick odd parity, 1 stop
--                     Test 18 : 6-bit data, stick odd parity, 2 stop
--                     Test 19 : 6-bit data, no parity, 1 stop
--                     Test 20 : 6-bit data, no parity, 2 stop
--                     Test 21 : 7-bit data, even parity, 1 stop
--                     Test 22 : 7-bit data, even parity, 2 stop
--                     Test 23 : 7-bit data, odd parity, 1 stop
--                     Test 24 : 7-bit data, odd parity, 2 stop
--                     Test 25 : 7-bit data, stick even parity, 1 stop
--                     Test 26 : 7-bit data, stick even parity, 2 stop
--                     Test 27 : 7-bit data, stick odd parity, 1 stop
--                     Test 28 : 7-bit data, stick odd parity, 2 stop
--                     Test 29 : 7-bit data, no parity, 1 stop
--                     Test 30 : 7-bit data, no parity, 2 stop
--                     Test 31 : 8-bit data, even parity, 1 stop
--                     Test 32 : 8-bit data, even parity, 2 stop
--                     Test 33 : 8-bit data, odd parity, 1 stop
--                     Test 34 : 8-bit data, odd parity, 2 stop
--                     Test 35 : 8-bit data, stick even parity, 1 stop
--                     Test 36 : 8-bit data, stick even parity, 2 stop
--                     Test 37 : 8-bit data, stick odd parity, 1 stop
--                     Test 38 : 8-bit data, stick odd parity, 2 stop
--                     Test 39 : 8-bit data, no parity, 1 stop
--                     Test 40 : 8-bit data, no parity, 2 stop
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.1 :| J.H.              :| 06/19/01  :| Support ispMACH 5000VG
--   V1.0 :| J.H.              :| 06/01/01  :| First Release
-- --------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity uart_tx_tb is
end uart_tx_tb;

architecture behavior of uart_tx_tb is 

  component Uart_top
    port(
      MR     : in  std_logic;
      MCLK   : in  std_logic;

      CS     : in  std_logic;
      RDn    : in  std_logic;
      WRn    : in  std_logic;
      ADSn   : in  std_logic;
      A      : in  std_logic_vector(2 downto 0);

      DIN    : in  std_logic_vector(7 downto 0);
      DOUT   : out std_logic_vector(7 downto 0);
      DDIS   : out std_logic;
      INTR   : out std_logic;

      SIN    : in  std_logic;
      RxRDYn : out std_logic;

      SOUT   : out std_logic;      
      TxRDYn : out std_logic;

      DCDn   : in  std_logic;
      CTSn   : in  std_logic;
      DSRn   : in  std_logic;
      RIn    : in  std_logic;    
      DTRn   : out std_logic;
      RTSn   : out std_logic
    );
  end component;

  -- Clock Frequency of Test
  --   MCLK_MHZ : frequency of MCLK
  --   PLLO_MHZ : frequency of PLL clk_out
  --              When the UART design is targeted to devices without
  --              PLL feature or the PLL feature is not used, PLLO_MHZ
  --              should be set to the same value of MCLK_MHZ.
  constant MCLK_MHZ : real := 28.4000;
  constant PLLO_MHZ : real := 71.0000;

  constant ONE_K_NS : time := 1000 ns;

  -- Clock Period Declaration
  --   MCLK_CLK_PERIOD : clock period of MCLK
  --   CLK_PEROID      : clock period of internal clock
  constant MCLK_CLK_PERIOD : time := ONE_K_NS / MCLK_MHZ;
  constant CLK_PERIOD      : time := ONE_K_NS / PLLO_MHZ;

  -- UART Registers Address Map
  constant RBR : std_logic_vector(2 downto 0) := "000";
  constant THR : std_logic_vector(2 downto 0) := "000";
  constant IER : std_logic_vector(2 downto 0) := "001";
  constant IIR : std_logic_vector(2 downto 0) := "010";
  constant LCR : std_logic_vector(2 downto 0) := "011";
  constant MCR : std_logic_vector(2 downto 0) := "100";
  constant LSR : std_logic_vector(2 downto 0) := "101";
  constant MSR : std_logic_vector(2 downto 0) := "110";

  -- TimeOut Definition
  constant WAIT_TIMEOUT : integer := 1000;

  -- This procedure performs a write cycle over the internal register
  procedure write_reg (
    addr        : in  std_logic_vector(2 downto 0);
    data        : in  std_logic_vector(7 downto 0);
    signal CS   : out std_logic;
    signal ADSn : out std_logic;
    signal WRn  : out std_logic;
    signal A    : out std_logic_vector(2 Downto 0);
    signal DIN  : out std_logic_vector(7 DownTo 0)) is
  begin
    wait for CLK_PERIOD;
    ADSn <= '0';
    wait for CLK_PERIOD;
    A <= addr;
    CS <= '1';
    wait for CLK_PERIOD;
    ADSn <= '1';
    wait for CLK_PERIOD;
    A <= (others => '1');
    CS <= '0';
    wait for (2*CLK_PERIOD);
    WRn <= '0';
    wait for CLK_PERIOD;
    DIN <= data;
    wait for CLK_PERIOD;
    WRn <= '1';
    wait for CLK_PERIOD;
    DIN <= (others => '1');
    wait for (2*CLK_PERIOD);
  end write_reg;

  -- This procedure performs a read cycle over the internal register
  procedure read_reg (
    addr        : in  std_logic_vector(2 downto 0);
    signal data : out std_logic_vector(7 downto 0);
    signal CS   : out std_logic;
    signal ADSn : out std_logic;
    signal RDn  : out std_logic;
    signal A    : out std_logic_vector(2 Downto 0);
    signal DOUT : in  std_logic_vector(7 Downto 0)) is
  begin
    wait for CLK_PERIOD;
    ADSn <= '0';
    wait for CLK_PERIOD;
    A <= addr;
    CS <= '1';
    wait for CLK_PERIOD;
    ADSn <= '1';
    wait for CLK_PERIOD;
    A <= (others => '1');
    CS <= '0';
    wait for (2*CLK_PERIOD);
    RDn <= '0';
    wait for (2*CLK_PERIOD);
    data <= DOUT;
    RDn <= '1';
    wait for (3*CLK_PERIOD);
  end read_reg;

  -- This procedure generates a serial frame for testing
  procedure sout_chk (
    numDataBits        : integer range 5 to 8;
    Txdata             : in std_logic_vector(7 downto 0);
    ParityBit          : in std_logic;
    stopBitLength      : real;
    parityBitExist     : boolean;
    constant cycleTime : in time;
    signal SOUT        : in std_logic) is
    variable i : integer;
  begin
    -- Wait for Start Bit
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for cycleTime/32;
        exit when SOUT = '0';
        i := i + 1;
      else
        assert (false) report"Start bit Generation Failed"
        severity failure;
      end if;
    end loop;
    -- Start Bit checking
    for i in 1 to 15 loop
      wait for cycleTime/16;
      assert SOUT = '0'
        report "Start bit too short"
        severity failure;
    end loop;
    -- Data Bits checking
    for dataBit in 0 to numDataBits-1 loop
      for i in 0 to 15 loop
        wait for cycleTime/16;
        assert SOUT = TxData(databit)
          report "Transmitted Data bits incorrect"
          severity failure;
      end loop;
    end loop;
    -- Parity Bit checking
    if (parityBitExist) then
      for i in 0 to 15 loop
        wait for cycleTime/16;
        assert SOUT = ParityBit
          report "Transmitted Parity bit incorrect"
          severity failure;
      end loop;
    end if;
    -- Stop Bit checking
    if (stopBitLength = 1.0) then
      for i in 0 to 15 loop
        wait for cycleTime/16;
        assert SOUT = '1'
          report "Transmitted 1 Stop bit incorrect"
          severity failure;
      end loop;
    elsif (stopBitLength = 1.5) then
      for i in 0 to 23 loop
        wait for cycleTime/16;
        assert SOUT = '1'
          report "Transmitted 1.5 Stop bit incorrect"
          severity failure;
      end loop;
    elsif (stopBitLength = 2.0) then
      for i in 0 to 31 loop
        wait for cycleTime/16;
        assert SOUT = '1'
          report "Transmitted 2 Stop bit incorrect"
          severity failure;
      end loop;
    else
      assert (false)
        report "Incorrect Stop bit length specified"
        severity failure;
    end if;
  end sout_chk;

  signal MR     : std_logic := '1';
  signal MCLK   : std_logic := '0';
  signal CS     : std_logic := '0';
  signal RDn    : std_logic := '1';
  signal WRn    : std_logic := '1';
  signal ADSn   : std_logic := '1';
  signal A      : std_logic_vector(2 downto 0);
  signal DIN    : std_logic_vector(7 downto 0);
  signal DOUT   : std_logic_vector(7 downto 0);
  signal DDIS   : std_logic;
  signal INTR   : std_logic;
  signal SIN    : std_logic;
  signal RxRDYn : std_logic;
  signal SOUT   : std_logic;
  signal TxRDYn : std_logic;
  signal DCDn   : std_logic;
  signal CTSn   : std_logic;
  signal DSRn   : std_logic;
  signal RIn    : std_logic;
  signal DTRn   : std_logic;
  signal RTSn   : std_logic;

  signal regData_readBack : std_logic_vector(7 downto 0);
  signal TestID           : integer := 0;

  signal PCLK   : std_logic := '0';

begin


-----------------------------------------------------------------------
-- UUT Instantiation
-----------------------------------------------------------------------
  uut: Uart_top port map(
    MR     => MR,
    MCLK   => MCLK,
    CS     => CS,
    RDn    => RDn,
    WRn    => WRn,
    ADSn   => ADSn,
    A      => A,
    DIN    => DIN,
    DOUT   => DOUT,
    DDIS   => DDIS,
    INTR   => INTR,
    SIN    => SIN,
    RxRDYn => RxRDYn,
    SOUT   => SOUT,
    TxRDYn => TxRDYn,
    DCDn   => DCDn,
    CTSn   => CTSn,
    DSRn   => DSRn,
    RIn    => RIn,
    DTRn   => DTRn,
    RTSn   => RTSn
  );


-- Master Clock Generator
  MCLK <= not MCLK after (MCLK_CLK_PERIOD/2);

-- PLL Clock Generator (for simulation purpose)
  PCLK <= not PCLK after (CLK_PERIOD/2);


-----------------------------------------------------------------------
-- SOUT Checking for UART Transmitter Functions Tests
-----------------------------------------------------------------------
  Sout_Chk_Proc: process
  begin

    wait for (10*CLK_PERIOD);
    
    -- Test 1 ----------------------------------------------------
    --   5-bit data, even parity, 1 stop
    sout_chk(5, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
    sout_chk(5, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
    sout_chk(5, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
    sout_chk(5, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);

    -- Test 2 ----------------------------------------------------
    --   5-bit data, even parity, 1.5 stop
    sout_chk(5, "01010101", '1', 1.5, True, CLK_PERIOD*16, SOUT);
    sout_chk(5, "10101010", '0', 1.5, True, CLK_PERIOD*16, SOUT);