?? uart_tx_tb.vhd
字號:
-- Test 10 ---------------------------------------------------
-- 5-bit data, stick odd parity, 1.5 stop
TestID <= 10;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 0, parity disabled
-- bit 2 : 1, 1.5 stop bit
-- bit 1 : 0, 5 data bit (bit[1-0]="00")
-- bit 0 : 0, 5 data bit (bit[1-0]="00")
write_reg (LCR,"00000100",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 11 ---------------------------------------------------
-- 6-bit data, even parity, 1 stop
TestID <= 11;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00011001",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 12 ---------------------------------------------------
-- 6-bit data, even parity, 2 stop
TestID <= 12;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 1, 2 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00011101",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 13 ---------------------------------------------------
-- 6-bit data, odd parity, 1 stop
TestID <= 13;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00001001",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 14 ---------------------------------------------------
-- 6-bit data, odd parity, 2 stop
TestID <= 14;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 0, odd parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 1, 2 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00001101",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 15 ---------------------------------------------------
-- 6-bit data, stick even parity, 1 stop
TestID <= 15;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 1, stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00111001",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 16 ---------------------------------------------------
-- 6-bit data, stick even parity, 2 stop
TestID <= 16;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 1, stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 1, 2 stop bit
-- bit 1 : 0, 6 data bit (bit[1-0]="01")
-- bit 0 : 1, 6 data bit (bit[1-0]="01")
write_reg (LCR,"00111101",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 17 ---------------------------------------------------
-- 6-bit data, stick odd parity, 1 stop
TestID <= 17;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
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