?? uart_int_tb.vhd
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-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
-- Lattice Semiconductor grants permission to use this code for use
-- in synthesis for any Lattice programmable logic product. Other
-- use of this code, including the selling or duplication of any
-- portion is strictly prohibited.
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
--
-- Project: Universal Asynchronous Receiver Transmitter
-- File: uart_int_tb.vhd
-- Title: uart_int_tb
-- Design Library: IEEE, generics
-- Dependencies: IEEE.std_logic_1164.all
-- IEEE.numeric_std.all
-- generics.components.all
-- Description: VHDL test bench for UART_top Prioritized Interrupt testing
-- ==========================================================
-- ====== Prioritized Interrupt Control Functions =====
-- ==========================================================
-- Priority Interrupt Type Interrupt Source Reset Control
-- Level
-- ==========================================================
-- Highest Receiver Line Overrun Error Reading LSR
-- Status Parity Error
-- Framing Error
-- BreakInt Error
-- ----------------------------------------------------------
-- Second Receiver Data Receiver Data Reading RBR
-- Available Available
-- ----------------------------------------------------------
-- Third Transmitter Transmitter Reading IIR
-- Hold Register Hold Register or
-- Empty Empty Writing THR
-- ----------------------------------------------------------
-- Lowest Modem Status Clear to Send Reading MSR
-- Data Set Ready
-- Ring Indicator
-- Data Carrier Detect
-- ==========================================================
-- There are 6 tests in the following combinations:
-- Test 1 : Level 1 interrupt test
-- Test 2 : Level 2 interrupt test
-- Test 3 : Level 3 interrupt test
-- Test 4 : Level 4 interrupt test
-- Test 5 : Mixed level 1,2 interrupt test
-- Test 6 : Mixed 1evel 1,2,3 interrupt test
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
-- Ver :| Author :| Mod. Date :| Changes Made:
-- V1.1 :| J.H. :| 06/19/01 :| Support ispMACH 5000VG
-- V1.0 :| D.W. & J.H. :| 06/01/01 :| First Release
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity uart_int_tb is
end uart_int_tb;
architecture behavior of uart_int_tb is
component Uart_top
port(
MR : in std_logic;
MCLK : in std_logic;
CS : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
ADSn : in std_logic;
A : in std_logic_vector(2 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
DDIS : out std_logic;
INTR : out std_logic;
SIN : in std_logic;
RxRDYn : out std_logic;
SOUT : out std_logic;
TxRDYn : out std_logic;
DCDn : in std_logic;
CTSn : in std_logic;
DSRn : in std_logic;
RIn : in std_logic;
DTRn : out std_logic;
RTSn : out std_logic
);
end component;
-- Clock Frequency of Test
-- MCLK_MHZ : frequency of MCLK
-- PLLO_MHZ : frequency of PLL clk_out
-- When the UART design is targeted to devices without
-- PLL feature or the PLL feature is not used, PLLO_MHZ
-- should be set to the same value of MCLK_MHZ.
constant MCLK_MHZ : real := 28.4000;
constant PLLO_MHZ : real := 71.0000;
constant ONE_K_NS : time := 1000 ns;
-- Clock Period Declaration
-- MCLK_CLK_PERIOD : clock period of MCLK
-- CLK_PEROID : clock period of internal clock
constant MCLK_CLK_PERIOD : time := ONE_K_NS / MCLK_MHZ;
constant CLK_PERIOD : time := ONE_K_NS / PLLO_MHZ;
-- UART Registers Address Map
constant RBR : std_logic_vector(2 downto 0) := "000";
constant THR : std_logic_vector(2 downto 0) := "000";
constant IER : std_logic_vector(2 downto 0) := "001";
constant IIR : std_logic_vector(2 downto 0) := "010";
constant LCR : std_logic_vector(2 downto 0) := "011";
constant MCR : std_logic_vector(2 downto 0) := "100";
constant LSR : std_logic_vector(2 downto 0) := "101";
constant MSR : std_logic_vector(2 downto 0) := "110";
-- TimeOut Definition
constant WAIT_TIMEOUT : integer := 1000;
-- This procedure performs a write cycle over the internal register
procedure write_reg (
addr : in std_logic_vector(2 downto 0);
data : in std_logic_vector(7 downto 0);
signal CS : out std_logic;
signal ADSn : out std_logic;
signal WRn : out std_logic;
signal A : out std_logic_vector(2 Downto 0);
signal DIN : out std_logic_vector(7 DownTo 0)) is
begin
wait for CLK_PERIOD;
ADSn <= '0';
wait for CLK_PERIOD;
A <= addr;
CS <= '1';
wait for CLK_PERIOD;
ADSn <= '1';
wait for CLK_PERIOD;
A <= (others => '1');
CS <= '0';
wait for (2*CLK_PERIOD);
WRn <= '0';
wait for CLK_PERIOD;
DIN <= data;
wait for CLK_PERIOD;
WRn <= '1';
wait for CLK_PERIOD;
DIN <= (others => '1');
wait for (2*CLK_PERIOD);
end write_reg;
-- This procedure performs a read cycle over the internal register
procedure read_reg (
addr : in std_logic_vector(2 downto 0);
signal data : out std_logic_vector(7 downto 0);
signal CS : out std_logic;
signal ADSn : out std_logic;
signal RDn : out std_logic;
signal A : out std_logic_vector(2 Downto 0);
signal DOUT : in std_logic_vector(7 Downto 0)) is
begin
wait for CLK_PERIOD;
ADSn <= '0';
wait for CLK_PERIOD;
A <= addr;
CS <= '1';
wait for CLK_PERIOD;
ADSn <= '1';
wait for CLK_PERIOD;
A <= (others => '1');
CS <= '0';
wait for (2*CLK_PERIOD);
RDn <= '0';
wait for (2*CLK_PERIOD);
data <= DOUT;
RDn <= '1';
wait for (3*CLK_PERIOD);
end read_reg;
-- This procedure generates a serial frame for testing
procedure sin_gen (
numDataBits : integer range 5 to 8;
data : in std_logic_vector(7 downto 0);
parity : in std_logic;
stopBitLength : real;
parityBitExist : boolean;
stopBitIsHigh : boolean;
constant cycleTime : in time;
signal SIN : out std_logic) is
begin
-- Start Bit
SIN <= '0';
wait for cycleTime;
-- Data Bits
for dataBit in 0 to numDataBits-1 loop
SIN <= data(dataBit);
wait for cycleTime;
end loop;
-- Parity Bit
if (parityBitExist) then
SIN <= parity;
wait for cycleTime;
end if;
-- Stop Bit(s)
if (stopBitIsHigh) then
SIN <= '1';
else
SIN <= '0'; -- for BREAK & Framing Error generation
end if;
wait for stopBitLength*cycleTime;
SIN <= '1';
end sin_gen;
signal MR : std_logic := '1';
signal MCLK : std_logic := '0';
signal CS : std_logic := '0';
signal RDn : std_logic := '1';
signal WRn : std_logic := '1';
signal ADSn : std_logic := '1';
signal A : std_logic_vector(2 downto 0);
signal DIN : std_logic_vector(7 downto 0);
signal DOUT : std_logic_vector(7 downto 0);
signal DDIS : std_logic;
signal INTR : std_logic;
signal SIN : std_logic;
signal RxRDYn : std_logic;
signal SOUT : std_logic;
signal TxRDYn : std_logic;
signal DCDn : std_logic;
signal CTSn : std_logic;
signal DSRn : std_logic;
signal RIn : std_logic;
signal DTRn : std_logic;
signal RTSn : std_logic;
signal regData_readBack : std_logic_vector(7 downto 0);
signal okToReceiveSIN : std_logic := '0';
signal TestID : integer := 0;
signal EOT : boolean := false;
signal intLevel : integer := 0;
begin
-----------------------------------------------------------------------
-- UUT Instantiation
-----------------------------------------------------------------------
uut: Uart_top port map(
MR => MR,
MCLK => MCLK,
CS => CS,
RDn => RDn,
WRn => WRn,
ADSn => ADSn,
A => A,
DIN => DIN,
DOUT => DOUT,
DDIS => DDIS,
INTR => INTR,
SIN => SIN,
RxRDYn => RxRDYn,
SOUT => SOUT,
TxRDYn => TxRDYn,
DCDn => DCDn,
CTSn => CTSn,
DSRn => DSRn,
RIn => RIn,
DTRn => DTRn,
RTSn => RTSn
);
-- Master Clock Generator
MCLK <= not MCLK after (MCLK_CLK_PERIOD/2);
-----------------------------------------------------------------------
-- SIN Generation for UART Receiver Functions Tests
-----------------------------------------------------------------------
SIN_proc: process
begin
-- SIN Initialization
SIN<= '1';
EOT <= False,
True after 50 ns;
-- Test 1 ----------------------------------------------------
-- Level 1 interrupt test
-- Receiver Line Status Interrupt test
wait until rising_edge(okToReceiveSIN);
EOT <= False;
sin_gen(8,"10101010",'0',1.0,false,true,CLK_PERIOD*16, SIN);
sin_gen(8,"01010110",'0',1.0,false,true,CLK_PERIOD*16, SIN);
EOT <= True;
-- Test 2 ----------------------------------------------------
-- Level 2 interrupt test
-- Receiver Data Available Interrupt test
wait until rising_edge(okToReceiveSIN);
EOT <= False;
sin_gen(8,"10010010",'1',1.0,true,true,CLK_PERIOD*16, SIN);
sin_gen(8,"10010011",'0',1.0,true,true,CLK_PERIOD*16, SIN);
EOT <= True;
-- Test 3 ----------------------------------------------------
-- Level 3 interrupt test
-- Transmitter Holding Register Empty Interrupt test
-- (Do nothing here for this test)
-- Test 4 ----------------------------------------------------
-- Level 4 interrupt test
-- MODEM Status Interrupt test
-- (Do nothing here for this test)
-- Test 5 ----------------------------------------------------
-- Mixed level 1,2 interrupt test
wait until rising_edge(okToReceiveSIN);
EOT <= False;
sin_gen(8,"10010010",'1',1.0,true,true,CLK_PERIOD*16, SIN);
sin_gen(8,"10010010",'0',1.0,true,true,CLK_PERIOD*16, SIN);
EOT <= True;
-- Test 6 ----------------------------------------------------
-- Mixed level 1,2,3 interrupt test
wait until rising_edge(okToReceiveSIN);
EOT <= False;
sin_gen(8,"10010010",'0',1.0,true,true,CLK_PERIOD*16, SIN);
sin_gen(8,"10010010",'1',1.0,true,true,CLK_PERIOD*16, SIN);
EOT <= True;
-- end of tests ----------------------------------------------
wait;
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