?? uart_rx_tb.vhd

?? lattice的串口仿真的程序
?? VHD
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    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00101010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 9 ----------------------------------------------------
    --   6-bit data receiving test, stick odd parity
    TestID <= 9;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00101001",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00101010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 10 ---------------------------------------------------
    --   6-bit data receiving test, no parity
    TestID <= 10;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 0, parity disabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00000001",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00101010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 11 ---------------------------------------------------
    --   7-bit data receiving test, even parity
    TestID <= 11;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00011010",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00101010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 12 ---------------------------------------------------
    --   7-bit data receiving test, odd parity
    TestID <= 12;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00001010",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
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?? 文件大小 43 K
?? 上傳用戶 joyman
?? 所屬分類(lèi) VHDL/FPGA/Verilog
??? 相關(guān)標(biāo)簽

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?? uart_rx_tb.vhd

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