Release 7.1i par H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.WSB::  Mon Oct 23 16:11:19 2006par -w -intstyle ise -ol std -t 1 test_map.ncd test.ncd test.pcf Constraints file: test.pcf.Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.   "test" is an NCD, version 3.1, device xc3s400, package pq208, speed -4Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)Device speed data version:  "PRODUCTION 1.35 2005-01-22".Device Utilization Summary:   Number of BUFGMUXs                  1 out of 8      12%   Number of External IOBs            65 out of 141    46%      Number of LOCed IOBs            48 out of 65     73%   Number of Slices                   71 out of 3584    1%      Number of SLICEMs                0 out of 1792    0%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Starting PlacerPhase 1.1Phase 1.1 (Checksum:989918) REAL time: 1 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs Phase 3.2.Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 1 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs Phase 6.8..Phase 6.8 (Checksum:9aba3b) REAL time: 1 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs Writing design to file test.ncdTotal REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Starting RouterPhase 1: 561 unrouted;       REAL time: 2 secs Phase 2: 488 unrouted;       REAL time: 2 secs Phase 3: 154 unrouted;       REAL time: 2 secs Phase 4: 0 unrouted;       REAL time: 2 secs WARNING:CLK Net:sdclk_OBUFmay have excessive skew because 1 NON-CLK pinsfailed to route using a CLK template.Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|          sdclk_OBUF |      BUFGMUX2| No   |   62 |  0.060     |  1.074      |+---------------------+--------------+------+------+------------+-------------+INFO:Par:340 -    The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 3 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage:  81 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file test.ncdPAR done!