// MAX+plus II Verilog Example
// LPM RAM Instantiation
// Copyright (c) 1997 Altera Corporation

module ram256x8 ( data, address, we, inclock, outclock, q);

   input [7:0]data;
   input [7:0]address;
   input we, inclock, outclock;
   output [7:0]q;

   lpm_ram_dq inst_1 (.q (q), .data(data), .address(address), 
                      .we(we), .inclock(inclock), .outclock(outclock));
       defparam inst_1.lpm_width = 8;
       defparam inst_1.lpm_widthad = 8;

endmodule