JDF E
// Created by ISE ver 1.0
PROJECT vgaout
DESIGN vgaout Normal
DEVKIT xc2s100-5tq144
DEVFAM spartan2
FLOW XST VHDL
STIMULUS vga_tbw.tbw Normal
STIMULUS sig_tbw.tbw Normal
MODULE vgacore.vhd
MODSTYLE vgacore Normal
MODULE vgasig.vhd
MODSTYLE vgasig Normal
MODULE colormap.vhd
MODSTYLE colormap Normal
[STRATEGY-LIST]
Normal=True, 1031971534
[Normal]
xilxBitgStart_Clk=xstvhd, SPARTAN2, Implementation.t_bitFile, 1032318492, JTAG Clock