?? fpq128.vhd
字號(hào):
--分頻器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fpq128 IS
PORT
( clk : IN std_logic;
bout : out std_logic);
END fpq128;
ARCHITECTURE fpq128_arc OF fpq128 Is
SIGNAL cnt1: std_logic;
begin
process(clk)
VARIABLE cnt : INTEGER RANGE 0 TO 128;
constant modulus:integer:=64;
begin
if (clk'event and clk='1') then
if cnt=modulus then
cnt:=0; cnt1<=not cnt1; bout<=cnt1;
end if;
cnt:=cnt+1;
end if;
end process;
end fpq128_arc;
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