---------------------------------------------------------------------------------   IT51 (Improved-T51)                                                     ----                                                                           ----   VERSION: 030723                                                         ----                                                                           ----   Contact: yfchen58@gmail.com                                             ----                                                                           -----------------------------------------------------------------------------------                                                                           ----  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       ----  Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)             ----                          Yung-Fu Chen (yfchen58@ms49.hinet.net)           ----                                                                           -----------------------------------------------------------------------------------  FETURE                                                                   ----     . IT51_top interface is similar to synopsys DW8051                    ----     . High-Performance 1-Cycle 8051                                       ----     . instruction compatible with standard DW8051                         ----     . 256 byte internal data memory                                       ----     . up to 64KB external data memory                                     ----     . up to 64KB internal program memory                                  ----     . export sfr-bus                                                      ----     . no dual-port memory used                                            ----     . no watch-dog timer                                                  ----     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           ----     . sleep mode support, refer to DW8051                                 ----     . no stop mode                                                        ----     . six external interrupt, refer to DW8051                             ----     . pass all DW8051 test-pattern                                        ----     . UART/Timer are not fully tested yet                                 ----     . no internal tri-state bus                                           ----     . 2-Cycle MUL Instruction                                             ----                                                                           -----------------------------------------------------------------------------------                                                                           ----  IT51_top (Interface Compatible with Synopsys DW8051)                     ----     |                                                                     ----     +-- IT51_core (Control Unit)                                          ----     |       |                                                             ----     |       +-- IT51_ALU (ALU)                                            ----     |               |                                                     ----     |               +-- IT51_MD (MUL/DIV)                                 ----     |                                                                     ----     +-- IT51_Glue (Glue Logic)                                            ----     |                                                                     ----     +-- IT51_TC01 (Timer/Counter-1)                                       ----     |                                                                     ----     +-- IT51_TC2 (Timer/Counter-2)                                        ----     |                                                                     ----     +-- IT51_UART (UART)                                                  ----                                                                           ----------------------------------------------------------------------------------- ============================================================================-- The original T51 license is listed below:-- ============================================================================---- 8051 compatible microcontroller core---- Version : 0218---- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)---- All rights reserved---- Redistribution and use in source and synthezised forms, with or without-- modification, are permitted provided that the following conditions are met:---- Redistributions of source code must retain the above copyright notice,-- this list of conditions and the following disclaimer.---- Redistributions in synthesized form must reproduce the above copyright-- notice, this list of conditions and the following disclaimer in the-- documentation and/or other materials provided with the distribution.---- Neither the name of the author nor the names of other contributors may-- be used to endorse or promote products derived from this software without-- specific prior written permission.---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE-- POSSIBILITY OF SUCH DAMAGE.---- Please report bugs to the author, but before you do so, please-- make sure that this is not a derivative work and that-- you have the latest version of this file.---- The latest version of this file can be found at:--	http://www.opencores.org/cvsweb.shtml/t51/---- Limitations :---- File history :---- ============================================================================library IEEE;use IEEE.std_logic_1164.all;library work;use work.IT51_Pack.all;entity IT51_Glue is    port(        Clk         : in std_logic;        Rst_n       : in std_logic;-- interrupt source        INT0        : in std_logic;  -- edge  or level, active low        INT1        : in std_logic;  -- edge  or level, active low        INT2        : in std_logic;  -- edge, active high        INT3        : in std_logic;  -- edge, active low        INT4        : in std_logic;  -- edge, active high        INT5        : in std_logic;  -- edge, active low--        RI          : in std_logic;        TI          : in std_logic;        OF0         : in std_logic;        OF1         : in std_logic;        OF2         : in std_logic;        IO_Wr       : in std_logic;        IO_Rd       : in std_logic;-- YFC >>        IO_CS       : out std_logic;-- <<        IO_Addr     : in std_logic_vector(6 downto 0);        IO_Addr_r   : in std_logic_vector(6 downto 0);        IO_WData    : in std_logic_vector(7 downto 0);        IO_RData    : out std_logic_vector(7 downto 0);        Int_Acc     : in std_logic_vector(10 downto 0);        Int_Trig    : out std_logic_vector(10 downto 0);        R0          : out std_logic;        R1          : out std_logic;        SMOD        : out std_logic;        TMOD_Sel    : out std_logic;        TL0_Sel     : out std_logic;        TL1_Sel     : out std_logic;        TH0_Sel     : out std_logic;        TH1_Sel     : out std_logic;        T2CON_Sel   : out std_logic;        RCAP2L_Sel  : out std_logic;        RCAP2H_Sel  : out std_logic;        TL2_Sel     : out std_logic;        TH2_Sel     : out std_logic;        SCON_Sel    : out std_logic;        SBUF_Sel    : out std_logic;        TMOD_Wr     : out std_logic;        TL0_Wr      : out std_logic;        TL1_Wr      : out std_logic;        TH0_Wr      : out std_logic;        TH1_Wr      : out std_logic;        T2CON_Wr    : out std_logic;        RCAP2L_Wr   : out std_logic;        RCAP2H_Wr   : out std_logic;        TL2_Wr      : out std_logic;        TH2_Wr      : out std_logic;        SCON_Wr     : out std_logic;        SBUF_Wr     : out std_logic;        Idle_n      : out std_logic;        Stop_n      : out std_logic    );end IT51_Glue;architecture rtl of IT51_Glue is    signal  IE         : std_logic_vector(7 downto 0);    signal  TCON       : std_logic_vector(7 downto 0);    signal  PCON       : std_logic_vector(7 downto 0);    alias   IDLE       : std_logic is PCON(0);    alias   STOP       : std_logic is PCON(1);    signal  Int0_r     : std_logic_vector(1 downto 0);    signal  Int1_r     : std_logic_vector(1 downto 0);    signal  Int2_r     : std_logic_vector(1 downto 0);    signal  Int3_r     : std_logic_vector(1 downto 0);    signal  Int4_r     : std_logic_vector(1 downto 0);    signal  Int5_r     : std_logic_vector(1 downto 0);    signal  Int_Trig_i : std_logic_vector(10 downto 0);    signal  EXIF       : std_logic_vector(7 downto 0);    signal  EIE        : std_logic_vector(7 downto 0);    signal  TMOD_Sel_i,    TMOD_Sel_r    : std_logic;    signal  TL0_Sel_i,     TL0_Sel_r     : std_logic;    signal  TL1_Sel_i,     TL1_Sel_r     : std_logic;    signal  TL2_Sel_i,     TL2_Sel_r     : std_logic;    signal  TH0_Sel_i,     TH0_Sel_r     : std_logic;    signal  TH1_Sel_i,     TH1_Sel_r     : std_logic;    signal  TH2_Sel_i,     TH2_Sel_r     : std_logic;    signal  T2CON_Sel_i,   T2CON_Sel_r   : std_logic;    signal  RCAP2L_Sel_i,  RCAP2L_Sel_r  : std_logic;    signal  RCAP2H_Sel_i,  RCAP2H_Sel_r  : std_logic;    signal  SCON_Sel_i,    SCON_Sel_r    : std_logic;    signal  SBUF_Sel_i,    SBUF_Sel_r    : std_logic;begin    R0       <= TCON(4);    R1       <= TCON(6);    SMOD     <= PCON(7);    Stop_n   <= not PCON(1);    Idle_n   <= not PCON(0);    Int_Trig <= Int_Trig_i;    -- Stop/IDLE    process (Rst_n, Clk)    begin        if Rst_n = '0' then            PCON <= "00110000";        elsif Clk'event and Clk = '1' then            if IO_Wr = '1' and IO_Addr_r = "0000111" then                PCON <= IO_WData;            end if;            if STOP = '0' then                if IDLE = '1' then                    if Int_Trig_i /= "00000000000" then                        IDLE   <= '0';                    end if;                end if;            end if;        end if;    end process;    -- Registers/Interrupts    process (IO_Addr, TCON, PCON, IE, EXIF, EIE)    begin        case IO_Addr is            when "0001000" => IO_RData <= TCON;            when "0000111" => IO_RData <= PCON;            when "0101000" => IO_RData <= IE;            when "0010001" => IO_RData <= EXIF;            when "1101000" => IO_RData <= EIE;            when others    => IO_RData <= "--------";        end case;        case IO_Addr is            when "0001000" => IO_CS <= '1';            when "0000111" => IO_CS <= '1';            when "0101000" => IO_CS <= '1';            when "0010001" => IO_CS <= '1';            when "1101000" => IO_CS <= '1';            when others    => IO_CS <= '0';        end case;    end process;    process (Rst_n, Clk)    begin        if Rst_n = '0' then            EIE    <= "11100000";            EXIF   <= "00001000";            IE     <= "00000000";            TCON   <= "00000000";            Int0_r <= "11";            Int1_r <= "11";            Int2_r <= "00";            Int3_r <= "11";            Int4_r <= "00";            Int5_r <= "11";        elsif Clk'event and Clk = '1' then            Int0_r <= Int0_r(0) & INT0;            Int1_r <= Int1_r(0) & INT1;