library  ieee;
use ieee.std_logic_1164.all;

entity divfre is
   generic(rate: integer range 0 to 255 :=10);
   port(fin:in std_logic;
       fout:out std_logic);
end divfre;

architecture behav of divfre is
   signal cnt:integer range 0 to 255 :=0;
begin  
   p1:process(fin)
   begin 
      if fin'event and fin='1' then
         if cnt = rate then
            cnt <= 1;
         else
            cnt <= cnt + 1;
         end if;
      end if;
   end process;
   fout <= '1' when cnt = rate else '0';
end behav;